Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 1092

Peripherals Routed Through the DPI
15 14
TWIRXINT
Receive FIFO Service
TWITXINT
Transmit FIFO Service
TWIMERR
Master Transfer Error
TWIMCOM
Master Transfer Complete
Figure A-153. TWIIRPTL Register
Table A-144. TWIIRPTL Register Bit Descriptions (W1X)
Bit Name
0 TWISINIT
1 TWISCOMP
2 TWISERR
3 TWISOVF
4 TWIMCOM
A-266
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13 12 11 10 9 8 7 6
Description
Slave Transfer Initiated.
0 = A transfer is not in progress. An address match has not occurred
since the last time this bit was cleared.
1 = The slave has detected an address match and a transfer has been
initiated.
Slave Transfer Complete.
0 = The completion of a transfer not detected
1 = The transfer is complete and either a stop, or a restart was
detected.
Slave Transfer Error.
0 = No errors detected
1 = An error has occurred. A restart or stop condition has occurred
during the data receive phase of a transfer.
Slave Overflow.
0 = No overflow detected
1 = The slave transfer complete (TWISCOMP) was set at the time a
subsequent transfer has acknowledged an address phase. The transfer
continues, however, it may be difficult to delineate data of one trans-
fer from another.
Master Transfer Complete.
0 = The completion of a transfer not detected
1 = The initiated master transfer is complete. In the absence of a
repeat start, the bus is released.
ADSP-214xx SHARC Processor Hardware Reference
5 4 3 2 1 0
TWISINIT
Slave Transfer Initiated
TWISCOMP
Slave Transfer Complete
TWISERR
Slave Transfer Error
TWISOVF
Slave Overflow