Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 1120

Register Listing
Register Mnemonic
DITCTL
S/PDIF Channel Status Registers
DITCHANA0
DITCHANA1
DITCHANA2
DITCHANA3
DITCHANA4
DITCHANA5
DITCHANB0
DITCHANB1
DITCHANB2
DITCHANB3
DITCHANB4
DITCHANB5
S/PDIF User Bit Status Registers
DITUSRBITA0
DITUSRBITA1
DITUSRBITA2
DITUSRBITA3
DITUSRBITA4
DITUSRBITA5
DITUSRBITB0
DITUSRBITB1
DITUSRBITB2
DITUSRBITB3
DITUSRBITB4
A-294
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Address Description
0x24A0 Digital Interface Transmit Control
0x24A1 Transmit CH0 Subframe A
0x24D4 Transmit CH1 Subframe A
0x24D5 Transmit CH2 Subframe A
0x24D6 Transmit CH3 Subframe A
0x24D7 Transmit CH4 Subframe A
0x24D8 Transmit CH5 Subframe A
0x24A2 Transmit CH0 Subframe B
0x24DA Transmit CH1 Subframe B
0x24DB Transmit CH2 Subframe B
0x24DC Transmit CH3 Subframe B
0x24DD Transmit CH4 Subframe B
0x24DE Transmit CH5 Subframe B
0x24E0 Transmit User Bit CH0 Subframe A
0x24E1 Transmit User Bit CH1 Subframe A
0x24E2 Transmit User Bit CH2 Subframe A
0x24E3 Transmit User Bit CH3 Subframe A
0x24E4 Transmit User Bit CH4 Subframe A
0x24E5 Transmit User Bit CH5 Subframe A
0x24E8 Transmit User Bit CH0 Subframe B
0x24E9 Transmit User Bit CH1 Subframe B
0x24EA Transmit User Bit CH2 Subframe B
0x24EB Transmit User Bit CH3 Subframe B
0x24EC Transmit User Bit CH4 Subframe B
ADSP-214xx SHARC Processor Hardware Reference
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0