RTC Initialization Status Register
The
RTC_INITSTAT
when the core comes out of reset.
CAL (R)
Calibration Status
PWDN (R)
Status of Power Down
Figure 22-7: RTC_INITSTAT Register Diagram
Table 22-11: RTC_INITSTAT Register Fields
Bit No.
(Access)
6:3
CAL
(R/NW)
2
PWDN
(R/NW)
1
DAYALMPND
(R/NW)
0
ALMPND
(R/NW)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register contains values of various status bits which can be used to check the status of RTC
15
14
13
12
11
10
0
0
0
0
0
0
31
30
29
28
27
26
0
0
0
0
0
0
Bit Name
Calibration Status.
Status of Power Down.
The RTC_INITSTAT.PWDN bit indicates the status of the RTC.
Day Alarm Pending.
The RTC_INITSTAT.DAYALMPND bit indicates that an alarm has occurred. This
indication is useful when the core has powered down or reset in the middle of opera-
tion. This bit is cleared when the
Alarm Pending.
The RTC_INITSTAT.ALMPND bit indicates that an alarm has occurred. This indi-
cation is useful when the core has powered down or reset in the middle of operation.
This bit is cleared when the
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
Description/Enumeration
0 Oscillator is powered down
1 Oscillator is running
0 Alarm occurred
1 No alarm occurred
RTC_INITSTAT
0 No alarm occurred
1 Alarm occurred
ADSP-SC58x RTC Register Descriptions
1
0
0
0
ALMPND (R)
Alarm Pending
DAYALMPND (R)
Day Alarm Pending
17
16
0
0
RTC_INITSTAT
register is read.
register is read.
22–17
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