Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 1172

Index
internal memory
DMA modifier (IDP_DMA_Mx)
registers, 11-20, 11-21
DMA modifier (IMSPx) registers, 2-5,
2-25
internal serial clock, setting, 10-29,
internal vs. external frame syncs,
interpolation, FIR filter,
interrputs
chained, 2-46
interrupt
enable interrupt on error (INTERR) bit,
15-26
interrupt and timer pins,
interrupt controller, DAI,
interrupts
accelerator, 6-64
channel priority, 2-48
conditions for generating interrupts,
10-46
data transfer, starting,
digital applications interface,
DMA slave, 4-19
(enable RX status interrupt) bit,
exception, 9-32
external memory booting,
FFT, 6-18
FFT accelerator, 6-18
FIFO to memory, 11-29
latch (IRPTL) register,
latch/mask (LIRPTL) registers,
link ports, 4-16
MAC status, FIR, 6-65
masking, 2-45
masking and latching,
peripheral timers, 16-18
polling, 2-45
priority, 2-48
I-14
www.BDTIC.com/ADI
(continued)
10-30
10-18
6-39
23-30
9-32
11-30
9-33
A-247
3-89
15-26
15-26
4-20
ADSP-214xx SHARC Processor Hardware Reference
interrupts
priority interrupt control registers
(PICR), B-4
restrictions, B-3
SPORTs, 10-49
SRC, 12-16
status, fir, 6-45
system, 9-32
transfer completion, 2-46
vector, sharing, 10-50
INVFSx (active low frame sync select for
frame sync) bits, 14-13
I/O interface to peripheral devices,
I/O processor, 2-24
address bus (IOA), 2-25
and addressing, 2-25
buffer, 2-36
DMA data, 2-32
bus priority, 2-42
bus priority, external port, 2-43, A-20,
A-46
bus structure, 2-30
chain assignment, 2-33
chained DMA, 2-11
chain pointer (CPSPI) register,
chain pointer registers,
configuring DMA, 2-51
count registers, 2-6, 2-27
DMA channel registers,
IDP buffer, 2-10
miscellaneous external port parameter
registers, 2-9
standard (non chained) DMA,
TCB memory allocation,
transfer types, 2-1, 2-2
ISSS (input service select) bit,
K
kernel boot timing, 23-23
(continued)
10-1
2-11
2-7
2-36
2-23
2-32
A-242