Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 1176

Index
optimization
SDRAM reads, example,
SDRAM reads, external port DMA
example, 3-43
SDRAM throughput,
OR, logical, 11-32
P
package availability, 1-2
packing
16 to 32-bit packing (PACK) bit, 10-22,
10-45, 10-50, A-154, A-159,
modes in IDP_PP_CTL, illustrated,
11-10
serial peripheral interface (PACKEN)
bit, A-236
packing instructions, 3-90
page size (SDRAM), A-55
parallel data acquisition port control
(IDP_PP_CTL) register,
parallel data acquisition port (PDAP),
11-32
parameter registers, DMA,
PCG
active low frame sync select for frame
sync (INVFSx) bits,
bypass mode, 14-13
clock A source (CLKASOURCE) bit,
A-193
clock input (CLKIN) pin,
clock input source enable
(CLKx_SOURCE_IOP) bit,
clock with external frame sync enable
(FSx_SYNC) bit, A-197
control (PCG_CTL_Ax) registers,
14-13, A-191, A-192
division ratios, 14-18
enable clock (ENCLKx) bit, A-191,
A-192
I-18
www.BDTIC.com/ADI
(continued)
3-42
3-117
A-163
A-179
2-36
14-13
17-5
A-197
ADSP-214xx SHARC Processor Hardware Reference
PCG
enable frame sync (ENFSx) bit, A-191,
A-192
frame sync A source (FSASOURCE) bit,
14-13, A-193
frame sync B source (FSBSOURCE) bit,
14-13, A-193
frame sync input source enable
(CLKx_SOURCE_IOP) bit,
frame sync with external frame sync
enable (FSx_SYNC) bit, A-197,
A-198
one shot frame sync A or B (STROBEx)
bits, 14-13
one shot option, 14-13
PCG_CTLA0 (control) register, A-191,
A-192
phase shift of frame sync,
pulse width for frame sync (PWFSx) bit,
A-194
pulse width (PCG_PW) register,
synchronization with the external clock,
14-20
PCI (program control interrupt) bit,
PDAP
enable (IDP_PDAP_EN) bit,
port mask bits (IDP_Pxx_PDAPMASK),
A-180
(rising or falling) clock edge
(IDP_PDAP_CLKEDGE) bit,
PDAP control (IDP_PDAP_CTL) register,
A-179
peripheral devices, I/O interface to,
peripherals
memory mapped, 3-10
peripheral timers
external event watchdog (EXT_CLK)
mode, 16-5, 16-15
input/output (TMRx) pin,
interrupts, 16-18
(continued)
A-197
14-16
14-13
2-13
A-181
A-181
10-1
16-5