Receive Bit-Slip Indication; Transmit Bit-Slip Control; Pll Pfd Feedback; Sdi Mode - Altera Cyclone IV Device Handbook

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Receive Bit-Slip Indication

The number of bits slipped in the word aligner for synchronization in manual
alignment mode is provided with the rx_bitslipboundaryselectout[4..0] signal.
For example, if one bit is slipped in word aligner to achieve synchronization, the
output on rx_bitslipboundaryselectout[4..0] signal shows a value of 1 (5'00001).
The information from this signal helps in latency calculation through the receiver as
the number of bits slipped in the word aligner varies at each synchronization.

Transmit Bit-Slip Control

The transmitter datapath supports bit-slip control to delay the serial data
transmission by a number of specified bits in PCS with
tx_bitslipboundaryselect[4..0] port. With 8- or 10-bit channel width, the
transmitter supports zero to nine bits of data slip. This feature helps to maintain a
fixed round trip latency by compensating latency variation from word aligner when
providing the appropriate values on tx_bitslipboundaryselect[4..0] port based on
values on rx_bitslipboundaryselectout[4..0] signal.

PLL PFD feedback

In Deterministic Latency mode, when transmitter input reference clock frequency is
the same as the low-speed clock, the PLL that clocks the transceiver supports PFD
feedback. When enabled, the PLL compensates for delay uncertainty in the low-speed
clock (tx_clkout in ×1 configuration or coreclkout in ×4 configuration) path relative
to input reference and the transmitter datapath latency is fixed relative to the
transmitter input reference clock.

SDI Mode

SDI mode provides the non-bonded (×1) transceiver channel datapath configuration
for HD- and 3G-SDI protocol implementations.
Cyclone IV GX transceivers configured in SDI mode provides the serialization and
deserialization functions that supports the SDI data rates as listed in
Table 1–24. Supported SDI Data Rates
SMPTE
Configuration
(1)
Standard
292M High definition (HD)
424M Third-generation (3G)
Note to Table 1–24:
(1) Society of Motion Picture and Television Engineers (SMPTE).
1
SDI functions such as scrambling/de-scrambling, framing, and cyclic redundancy
check (CRC) must be implemented in the user logic.
Cyclone IV Device Handbook,
Volume 2
FPGA Fabric-to-
Data Rate (Mbps)
Transceiver Width
1483.5
1485
2967
2970
Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
Table
Byte SERDES Usage
20-bit
10-bit Not used
20-bit
10-bit Not used
20-bit
February 2015 Altera Corporation
1–24.
Used
Used
Used