Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 1190

Index
UART
sampling point, 20-11
standard, 20-1
timers, 20-6
UART bits
9-bit RX enable (RX9),
9-bit TX enable (TX9),
address detect enable (UARTAEN),
A-250
DMA TX/RX control,
DMA TX/RX status,
enable receive buffer full interrupt
(UARTRBFIE), A-246
enable transmit buffer empty interrupt
(UARTTBEIE), A-246
interrupt enable, A-247
pack data, 20-8
packing enable (PACK),
pin status (UARTPSTx),
program controlled interrupt bit (PCI),
20-22
synch data packing in RX
(UARTPKSYN), A-250
THR register empty (UARTTHRE),
A-245
UARTNOINT (pending interrupt),
A-248
UARTSTAT (interrupt),
UART registers
divisor latch register
(UARTxDLL), 20-4,
divisor latch (UARTxDLH), 20-4,
A-249
interrupt enable register (UARTxIER),
A-246
interrupt identification register
(UARTxIIR), A-247
line control register (UARTxLCR),
A-243
line status register (UARTxLSR),
I-32
www.BDTIC.com/ADI
(continued)
A-250
A-250
A-251
A-252
A-250
A-251
A-248
A-249
A-245
ADSP-214xx SHARC Processor Hardware Reference
receive buffer register (UARTxRBR),
20-11
transmit holding (UARTxTHR),
transmit shift register (UART_TSR),
20-10
UARTxDLH (divisor latch register),
20-4, A-249
UARTxDLL (divisor latch register),
20-4, A-249
UARTxIER (interrupt enable register),
A-246
UARTxIIR (interrupt identification
register), A-247
UARTxLCR (line control register),
A-243
UARTxLSR (line status register),
UARTxRBR (receive buffer register),
20-11
UARTxTHR (transmit holding register),
20-10
UARTxTSR (transmit shift register),
20-10
V
VCO
bypass clock, 22-7
clock, 22-5
examples, clock management,
output clock, 22-5
W
wait states, enabling (WS bit), A-22,
warnings and cautions
DMA transfers, 2-28
I/O processor, 2-28
SPORTs, 10-42
watchdog function, timer,
watchdog timer
clocking, 19-4
20-10
A-245
22-15
A-49
16-19