Table 24-6: ACM_CTL Register Fields (Continued)
Bit No.
(Access)
6:5
TRGSEL1
(R/W)
4:3
TRGSEL0
(R/W)
2
TMR1EN
(R/W)
1
TMR0EN
(R/W)
0
EN
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
Trigger Select TMR1.
The ACM_CTL.TRGSEL1 bits select the external trigger for ACM TMR1.
Trigger Select TMR0.
The ACM_CTL.TRGSEL0 bits select the external trigger for ACM TMR0.
TMR1 Enable.
The ACM_CTL.TMR1EN bit enables ACM TMR1.
TMR0 Enable.
The ACM_CTL.TMR0EN bit enables ACM TMR0.
ACM Enable.
The ACM_CTL.EN bit enables ACM operation.
ADSP-SC58x ACM Register Descriptions
Description/Enumeration
0 Trigger 0 (ACM_T0 Pin)
1 Trigger 1 (ACM_T1 Pin)
2 Trigger 2 (Trigger Input 2 - TRU Slave)
3 Trigger 3 (Trigger Input 3 - TRU Slave)
0 Trigger 0 (ACM_T0 Pin)
1 Trigger 1 (ACM_T1 Pin)
2 Trigger 2 (Trigger Input 2 - TRU Slave)
3 Trigger 3 (Trigger Input 3 - TRU Slave)
0 Disable ACM TMR1
1 Enable ACM TMR1
0 Disable ACM TMR0
1 Enable ACM TMR0
0 Disable ACM
1 Enable ACM
24–25
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