Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1197

ADSP-SC58x ACM Register Descriptions
Event N Order Register
The
ACM_EVORD[n]
data captures at a stretch. The
completes in the trigger cycle.
ORD (R)
Order of Event Completion
EVSTAT (R)
Event Status
Figure 24-18: ACM_EVORD[n] Register Diagram
Table 24-9: ACM_EVORD[n] Register Fields
Bit No.
(Access)
17 EVSTAT
(R/NW)
16 MEVSTAT
(R/NW)
7:0 ORD
(R/NW)
24–30
registers hold the ADC data capture event order. These registers can store the order of 256
ACM_EVORD[n]
15 14 13 12 11 10
0 0 0 0 0 0
31 30 29 28 27 26
0 0 0 0 0 0
Bit Name
Event Status.
The ACM_EVORD[n].EVSTAT bit reflects the state of the corresponding event bit
in the
Missed Event Status.
The ACM_EVORD[n].MEVSTAT bit reflects the state of the corresponding event bit
in the
Order of Event Completion.
The ACM_EVORD[n].ORD bits indicate the order of event completion. Zero indi-
cates the first event completed (after the ACM is enabled or after the
ACM_CTL.ORST bit is set) and 255 indicates the 256th event completed.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
registers also have status bits indicating whether an event misses or
9 8 7 6 5 4 3 2
0 0 0 0 0 0 0 0
25 24 23 22 21 20 19 18
0 0 0 0 0 0 0 0
Description/Enumeration
register.
ACM_EVSTAT
register.
ACM_MEVSTAT
0 1st Event Completed
1 2nd Event Completed
255 256th Event Completed
1 0
0 0
17 16
0 0
MEVSTAT (R)
Missed Event Status