Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1194

Event Complete Interrupt Mask Register
The register enables interrupts corresponding to status bits in the
ACM_EVMSK
in the ACM_EVMSK register is set (=1), an interrupt generates when the corresponding event complete bit in the
ACM_EVSTAT register is set.
EV15 (R/W)
Event 15 Interrupt Enable
EV14 (R/W)
Event 14 Interrupt Enable
EV13 (R/W)
Event 13 Interrupt Enable
EV12 (R/W)
Event 12 Interrupt Enable
EV11 (R/W)
Event 11 Interrupt Enable
EV10 (R/W)
Event 10 Interrupt Enable
EV9 (R/W)
Event 9 Interrupt Enable
EV8 (R/W)
Event 8 Interrupt Enable
IECOM1 (R/W)
Event Complete 1 Interrupt Enable
Figure 24-17: ACM_EVMSK Register Diagram
Table 24-8: ACM_EVMSK Register Fields
Bit No.
(Access)
17 IECOM1
(R/W)
16 IECOM0
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15 14 13 12 11 10 9
0 0 0 0 0 0 0
31 30 29 28 27 26 25 24
0 0 0 0 0 0 0
Bit Name
Event Complete 1 Interrupt Enable.
Event Complete 0 Interrupt Enable.
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
Description/Enumeration
0 Disable (Mask) Interrupt
1 Enable (Unmask) Interrupt
0 Disable (Mask) Interrupt
1 Enable (Unmask) Interrupt
ADSP-SC58x ACM Register Descriptions
register. When a bit
ACM_EVSTAT
0
0
EV0 (R/W)
Event 0 Interrupt Enable
EV1 (R/W)
Event 1 Interrupt Enable
EV2 (R/W)
Event 2 Interrupt Enable
EV3 (R/W)
Event 3 Interrupt Enable
EV4 (R/W)
Event 4 Interrupt Enable
EV5 (R/W)
Event 5 Interrupt Enable
EV6 (R/W)
Event 6 Interrupt Enable
EV7 (R/W)
Event 7 Interrupt Enable
0
IECOM0 (R/W)
Event Complete 0 Interrupt Enable
24–27