Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1191

ADSP-SC58x ACM Register Descriptions
Table 24-6: ACM_CTL Register Fields (Continued)
Bit No.
(Access)
13 AOREN
(R/W)
12 ORST
(R/W)
11 CLKMOD
(R/W)
10 CLKPOL
(R/W)
9 CSPOL
(R/W)
8 TRGPOL1
(R/W)
7 TRGPOL0
(R/W)
24–24
Bit Name
Automatic Order Reset Enable.
The ACM_CTL.AOREN bit enables automatic reset of the event order
(ACM_EVORD[n]) registers, based on the selected timer trigger. The
ACM_CTL.OTSEL bit selects the trigger.
Order Register Reset.
The ACM_CTL.ORST bit resets the event order (ACM_EVORD[n]) register value to
0. This bit auto-clears to 0 after the
ADC Clock Mode.
The ACM_CTL.CLKMOD bit selects gated clock mode (ACM_CLK is gated when the
ADC CS is inactive) or continuous (ACM generates continuous ACM_CLK).
Clock Polarity.
The ACM_CTL.CLKPOL bit selects whether the rising or falling edge of ACM_CLK
comes after ADC CS becomes active.
Chip Select Polarity.
The ACM_CTL.CSPOL bit selects whether ADC CS is active high or low.
Trigger Polarity TMR1.
The ACM_CTL.TRGPOL1 bit selects whether the trigger polarity for ACM TMR1
occurs on the falling or rising edge.
Trigger Polarity TMR0.
The ACM_CTL.TRGPOL0 bit selects whether the trigger polarity for ACM TMR0
occurs on the falling or rising edge.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
0 Disable Automatic Order Reset
1 Enable Automatic Order Reset
ACM_EVORD[n] registers clear.
0 Continuous Clock Mode
1 Gated Clock Mode
0 Falling Edge of Clock After CS
1 Rising Edge of Clock After CS
0 Active Low CS
1 Active High CS
0 Rising Edge Trigger
1 Falling Edge Trigger
0 Rising Edge Trigger
1 Falling Edge Trigger