Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1190

Control Register
The register enables and selects the various modes of operation of the ACM.
ACM_CTL
EPS (R/W)
External Peripheral Select
OTSEL (R/W)
Order Trigger Select
AOREN (R/W)
Automatic Order Reset Enable
ORST (R/W)
Order Register Reset
CLKMOD (R/W)
ADC Clock Mode
CLKPOL (R/W)
Clock Polarity
CSPOL (R/W)
Chip Select Polarity
Figure 24-15: ACM_CTL Register Diagram
Table 24-6: ACM_CTL Register Fields
Bit No.
(Access)
15 EPS
(R/W)
14 OTSEL
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15 14 13 12 11
0 0 0 0 0
31 30 29 28 27
0 0 0 0 0
Bit Name
External Peripheral Select.
The ACM_CTL.EPS bit selects whether the ACM interfaces to half SPORT A or half
SPORT B.
Order Trigger Select.
The ACM_CTL.OTSEL bit selects whether TMR0 or TMR1 triggers a reset of the
event order (ACM_EVORD[n]) registers. This bit is applicable only if the
ACM_CTL.AOREN bit is set.
10 9 8 7 6 5 4 3
0 0 0 0 0 0 0 0
26 25 24 23 22 21 20 19
0 0 0 0 0 0 0 0
Description/Enumeration
0 Half SPORT A Interfaces to ACM
1 Half SPORT B Interfaces to ACM
0 ACM TMR0 Triggers Reset of Order Registers
1 ACM TMR1 Triggers Reset of Order Registers
ADSP-SC58x ACM Register Descriptions
2 1 0
0 0 0
EN (R/W)
ACM Enable
TMR0EN (R/W)
TMR0 Enable
TMR1EN (R/W)
TMR1 Enable
TRGSEL0 (R/W)
Trigger Select TMR0
TRGSEL1 (R/W)
Trigger Select TMR1
TRGPOL0 (R/W)
Trigger Polarity TMR0
TRGPOL1 (R/W)
Trigger Polarity TMR1
18 17 16
0 0 0
24–23