Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1193

ADSP-SC58x ACM Register Descriptions
Event N Control Register
The
ACM_EVCTL[n]
These control registers each have an event enable bit, that permits a selective enable of a particular event.
Do not program the
ACM_EVCTL[n]
and re-program this register after all the events are complete (ACM_STAT.ECOM1 or ACM_STAT.ECOM0 bit is
set). If no events are enabled in this register (for example, all ACM_EVCTL[n].ENAEV bits =0, and the
ACM_STAT.ECOM0 or ACM_STAT.ECOM1 bits are set) and an interrupt generates (if unmasked) a trigger is ap-
plied with the Timer enabled.
EPF (R/W)
Event Parameter Field
Figure 24-16: ACM_EVCTL[n] Register Diagram
Table 24-7: ACM_EVCTL[n] Register Fields
Bit No.
(Access)
5:1 EPF
(R/W)
0 ENAEV
(R/W)
24–26
registers each hold the ADC control value corresponding to the event related to the register.
register when an event is active. Program this register before setting trigger
15 14 13 12 11
0 0 0 0 0
31 30 29 28 27
0 0 0 0 0
Bit Name
Event Parameter Field.
The ACM_EVCTL[n].EPF bits select values for the ADC control pins
(ACM_A[n]. These values are output when the enabled event occurs. Selection of
ACM_EVCTL[n].EPF values are based on the type of ADC, usage mode, and other
items. For more information, see the operating modes section. All
ACM_EVCTL[n].EPF bits have the same external pin timing.
Enable Event.
The ACM_EVCTL[n].ENAEV bit causes a sampling event to occur based on the
controls selected by the ACM_EVCTL[n].EPF bit field when an event (time com-
parison match or other external trigger) occurs. If disabled, the corresponding event
has no significance, and the control values are not used.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
10 9 8 7 6 5 4 3
0 0 0 0 0 0 0 0
26 25 24 23 22 21 20 19
0 0 0 0 0 0 0 0
Description/Enumeration
0 Disable Event
1 Enable Event
2 1 0
0 0 0
ENAEV (R/W)
Enable Event
18 17 16
0 0 0