Register Descriptions - Freescale Semiconductor PowerQUICC MPC885 Reference Manual

Memory Controller
15.3.6 Memory Bank Protection Status
The memory controller status register (MSTAT) reports write-protect violations for all eight banks. This
protection provided through BRx[WP], is intended for detection of erroneous accesses made by DMA
from peripherals. More sophisticated protection is provided for accesses from the core by the MMU, as
described in Chapter 8, "Memory Management Unit."
15.3.7 UPM-Specific Registers
The machine x mode registers (MxMR) define most of the global features for UPMs. The memory
command and memory data registers (MCR and MDR) initialize the UPM's RAM array. MCR[MAD] is
the index into the 64-word RAM array for the MDR.
The memory address register (MAR) specifies the address to be driven on the external bus when a UPM
pattern is software-initiated by issuing a
The memory periodic timer prescaler register (MPTPR) defines the divisor of the external bus clock used
as the memory periodic timer input.
15.3.8 GPCM-Specific Registers
There are no GPCM-specific registers. All GPCM characteristics are defined in the subfields of individual
BRx and ORx registers.
15.4

Register Descriptions

The following sections describe the registers used by the memory controller.
15.4.1 Base Registers (BR x )
The base registers (BR0–BR7) contain the base address and address types that the memory controller uses
to compare the value on the address bus with the current address accessed. It also includes a memory
attribute and selects the machine for memory operation handling.
15-8
command in the MCR.
RUN
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Figure 15-5 shows the BRx register.
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