Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 378

External Bus Interface
Signal Pins I/O
BURST 1
Burst Transfer
TSIZ[0:1] 2
Transfer Size
AT[0:3] 4
Address Type
RSV 1
Reservation
Transfer
PTR 1
Program Trace
BDIP 1
Burst Data in
Progress
TS 1
Transfer Start
STS 1
Special Transfer
Start
KR/RETRY 1
Kill Reservation/
Retry
13-4
Table 13-1. MPC885 Signal Overview (continued)
1
O Driven by the MPC885 along with the address when it owns the external bus. Driven low
indicates that a burst transfer is in progress. Driven high indicates that the current
transfer is not a burst.
I Sampled by the MPC885 when an external device initiates a transaction and the
memory controller was configured to handle external master accesses.
O Driven by the MPC885 along with the address when it owns the external bus. Specifies
the data transfer size for the transaction.
I Sampled by the MPC885 when an external device initiates a transaction and the
memory controller was configured to handle external master accesses.
O Driven by the MPC885 along with the address when it owns the external bus. Indicates
additional information about the address on the current transaction.
O Driven by the MPC885 along with the address when it owns the external bus. Indicates
additional information about the address on the current transaction.
O Driven by the MPC885 along with the address when it owns the external bus. Indicates
additional information about the address on the current transaction.
O Driven by the MPC885 when it owns the external bus as part of the burst protocol.
Asserted indicates that the second beat in front of the current one is requested by the
master. Negated before the burst transfer ends to abort the burst data phase.
Transfer Start
O Driven by the MPC885 when it owns the external bus. Indicates the start of a transaction
on the external bus.
I Sampled by the MPC885 when an external device initiates a transaction and the
memory controller was configured to handle external master accesses.
O Driven by the MPC885 when it owns the external bus. Indicates the start of a transaction
on the external bus or signals the beginning of an internal transaction in show cycle
mode.
Reservation Protocol
I If the core initiates a bus cycle by executing a stwcx. to a nonlocal bus on which the
memory reservation is lost, the nonlocal bus uses this signal to back-off the cycle. See
Section 13.4.9, "Memory Reservation."
For regular transactions, the slave device drives this signal to indicate that the MPC885
must relinquish the bus and retry the cycle.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Freescale Semiconductor