Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 751

Data length and buffer pointer fields are described in
length represents the number of octets the CP writes into this buffer, including the BCS. For BISYNC
mode, clear these bits. It is incremented each time a received character is written to the buffer.
26.13 SCC BISYNC Transmit BD (TxBD)
The CP arranges data to be sent on an SCC channel in buffers referenced by the channel TxBD table. The
CP uses BDs to confirm transmission or indicate errors so the core knows buffers have been serviced. The
user configures status and control bits before transmission, but the CP sets them after the buffer is sent.
0 1
Offset + 0 R —
Offset + 2
Offset + 4
Offset + 6
Table 26-12 describes SCC BISYNC TxBD status and control fields.
Table 26-12. SCC BISYNC TxBD Status and Control Field Descriptions
Bits Name
0 R Ready
0 The buffer is not ready for transmission. The current BD and buffer can be updated. The CP
clears R after the buffer is sent or after an error condition.
1 The user-prepared buffer has not been sent or is being sent. This BD cannot be updated while
R = 1.
1 — Reserved, should be cleared.
2 W Wrap (last BD in table)
0 Not the last BD in the table
1 Last BD in the table. After this buffer is used, the CP sends data using the first BD that TBASE
points to. The number of TxBDs in this table is determined only by the W bit.
3 I Interrupt
0 No interrupt is generated after this buffer is serviced.
1 SCCE[TXB] or SCCE[TXE] is set after the CP services this buffer, which can cause an interrupt.
4 L Last in message
0 The last character in the buffer is not the last character in the current block.
1 The last character in the buffer is the last character in the current block. The transmitter enters
and stays in normal mode after sending the last character in the buffer and the BCS, if enabled.
5 TB Transmit BCS. Valid only when the L bit is set
0 Send an SYN1–SYN2 or idle sequence (specified in GSMR_H[RTSM]) after the last character in
the buffer.
1 Send the BCS sequence after the last character. The controller also resets the BCS generator
after sending the BCS.
Freescale Semiconductor
2 3 4 5 6
W I L TB CM
Tx Data Buffer Pointer
Figure 26-7. SCC BISYNC TxBD
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Section 21.3, "SCC Buffer Descriptors (BDs)."
7 8 9 10 11
BR TD TR B
Data Length
Description
SCC BISYNC Mode
Data
13 14 15
— UN CT
26-13