Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 162

MPC8xx Core Register Set
XER bits are described in
Bits Name
0 SO Summary overflow. Set when an instruction (except mtspr) sets the overflow bit (OV). When set,
SO remains set until it is cleared by an mtspr(XER) or an mcrxr instruction. It is not altered by
compare instructions or other instructions (except mtspr(XER) and mcrxr) that cannot overflow.
1 OV Overflow. Set to indicate that an overflow occurred during execution of an instruction. Add, subtract
from, and negate instructions with OE = 1 set OV if the carry out of the msb is not equal to the carry
out of the msb + 1 and clear it otherwise. Multiply low and divide instructions with OE = 1 set OV if
the result cannot be represented in 32 bits (mullw, divw, divwu) and clear it otherwise. The OV bit
is not altered by compare instructions that cannot overflow (except mtspr(XER) and mcrxr).
2 CA Carry. Set during execution of the following instructions:
• Add carrying, subtract from carrying, add extended, and subtract from extended instructions set
CA if there is a carry out of the msb, and clear it otherwise.
• Shift right algebraic instructions set CA if any 1 bits have been shifted out of a negative operand,
and clear it otherwise.
The CA bit is not altered by compare instructions, nor by other instructions that cannot carry (except
shift right algebraic, mtspr(XER), and mcrxr).
3–24 — Reserved
25–31 BCNT Specifies the number of bytes to be transferred by a Load String Word Indexed (lswx) or Store String
Word Indexed (stswx) instruction.
Although divide instructions have a relatively long latency, they can update XER[OV] after one cycle.
Therefore, data dependency on the XER is limited to one cycle, although the divide instruction latency can
be a maximum of 11 clocks.
4.1.1.1.4 Time Base Registers
The time base registers (TBU and TBL) are described in
"Clocks and Power Control."
with the time base, but one is implemented in the MPC885.
4.1.2 PowerPC Registers—Supervisor Registers
All supervisor-level registers implemented on the MPC885 are SPRs, except for the machine state register
(MSR), described in Table
Description
Machine state register
4-4
Table 4-4.
Table 4-4. XER Field Definitions
The PowerPC architecture does not define an exception associated directly
4-5.
Table 4-5. Supervisor-Level PowerPC Registers
Name Reference/Section
MSR See Section 4.1.2.3.1, "Machine State Register (MSR)."
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Section 10.9, "Timebase," and in Chapter 14,
Serialize Access
Write fetch sync
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