Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 257

Table 8-7 describes MI_CTR fields.
Bits Name
0 GPM Group protection mode
0 Default mode
1 Domain manager mode
1 PPM Page protection mode. Valid regardless of whether translation is enabled. If translation is
enabled, PPM determines how M x _RPN is interpreted. See
0 Page resolution of protection
1 1-Kbyte resolution of protection for 4-Kbyte pages
2 CIDEF Default value for instruction cache-inhibit attribute when the IMMU is disabled (MSR[IR] = 0)
0 Caching is allowed.
1 Caching is inhibited.
3 — Reserved. Ignored on write, returns 0 on read.
4 RSV4I Reserve four ITLB entries. See
0 ITLB_INDX decremented modulo 32
1 ITLB_INDX decremented modulo 28
5 — Reserved. Ignored on write, returns 0 on read.
6 PPCS Privilege/user state compare mode
0 Ignore user/supervisor state during address compare
1 Account for user/supervisor state according to MI_RPN[24–27]
7–18 — Reserved. Ignored on write, returns 0 on read.
19–23 ITLB_INDX ITLB index. Points to the ITLB entry to be loaded. Decremented every ITLB update
24–31 — Reserved. Ignored on write, returns 0 on read.
8.8.2 DMMU Control Register (MD_CTR)
The DMMU control register (MD_CTR), shown in
0 1
Field GPM PPM CIDEF WTDEF RS4VD TWAM PPCS
Reset
R/W
16
Field —
Reset
R/W
SPR
Freescale Semiconductor
Table 8-7. MI_CTR Field Descriptions
Section 8.10.2, "Locking TLB Entries."
2 3 4 5
0000_0 1
18 19
DTLB_INDX
Figure 8-7. DMMU Control Register (MD_CTR)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Table 8-12
Figure 8-7, controls DMMU operation.
6 7
0 0_0000_0000
R/W
23 24
0x0000
R/W
792
Memory Management Unit
and Table 8-13.
15
—
31
—
8-15