Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 324

Reset
Figure 11-7 shows the configuration data sampling timing relative to HRESET and CLKOUT.
0 1
CLKOUT
HRESET
RSTCONF
Data
Sample Data
Configuration
Figure 11-7. Reset Configuration Sampling Timing Requirements
11.3.1.1 Hard Reset Configuration Word
The hard reset configuration word is sampled from the data bus. These bits determine the default values
of the corresponding bits in the SIUMCR, IMMR, and MSR.
0 1
Field EARB IIP BBE BDIS
Default
16
Field
Default
NOTE: The default value is due to the internal pull-down resistor on the data bus.
Table 11-3 describes hard reset configuration word fields.
Table 11-3. Hard Reset Configuration Word Field Descriptions
Bits Name
0 EARB External arbitration. If this bit is set, external arbitration is assumed; if cleared, internal arbitration is
performed. See
1 IIP Initial interrupt prefix. Defines the initial value of the MSR[IP] which defines the interrupt table
location. If IIP is cleared (default), the MSR[IP] initial value is one; if it is set, the MSR[IP] initial value
is zero. See
11-8
2 3 4 5 6 7
Reset Configuration Word
Maximum Setup Time of
Reset Recognition
2 3 4 5 6
BPS —
0000_0000_0000_0000
0000_0000_0000_0000
Figure 11-8. Hard Reset Configuration Word
Section 10.4.2, "SIU Module Configuration Register (SIUMCR)."
Section 4.1.2.3.1, "Machine State Register (MSR)."
MPC885 PowerQUICC Family Reference Manual, Rev. 2
8 9 10 11 12 13
Maximum Time of
Reset Recognition
Sample Data
Configuration
7 8 9 10 11
ISB DBGC DBPC
—
Description
14 15 16 17
Sample Data
Configuration
12 13 14 15
EBDF CLES
31
Freescale Semiconductor