Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 845

Table 30-9 describes the TxBD status and control fields.
Table 30-9. SPI TxBD Status and Control Field Descriptions
Bits Name
0 R Ready
0 The buffer is not ready to be sent. This BD or its buffer can be modified. The CPM clears R (unless
RxBD[CM] is set) after the buffer is sent (unless RxBD[CM] is set) or an error occurs.
1 The buffer is ready for transmission or is being sent. The BD cannot be modified once R is set.
1 — Reserved, should be cleared.
2 W Wrap (last BD in TxBD table)
0 Not the last BD in the table
1 Last BD in the table. After this buffer is used, the CPM receives incoming data using the BD
pointed to by TBASE (top of the table). The number of BDs in this table is determined only by the
W bit.
3 I Interrupt
0 No interrupt is generated after this buffer is processed if an error does not occur.
1 SPIE[TXB] or SPIE[TXE] are set when this buffer is processed and causes interrupts if not
masked.
Note that this bit does not mask SPIE[TXE].
4 L Last
0 This buffer does not contain the last character of the message.
1 This buffer contains the last character of the message.
5 — Reserved, should be cleared.
6 CM Continuous mode. Valid only when the SPI is in master mode. In slave mode, it should be cleared.
0 Normal operation
1 The CPM does not clear TxBD[R] after this BD is closed, allowing the buffer to be resent
automatically when the CPM next accesses this BD.
7–13 — Reserved, should be cleared.
14 UN Underrun. Indicates that the SPI encountered a transmitter underrun condition while sending the
buffer. This error occurs only when the SPI is in slave mode. The SPI updates UN after it sends the
buffer.
15 ME Multimaster error. Indicates that this buffer is closed because SPISEL was asserted when the SPI
was in master mode. An arbitration problem occurred between devices on the SPI bus. The SPI
updates ME after sending the buffer.
30.8 SPI Master Programming Example
The following sequence initializes the SPI to run at a high speed in master mode:
1. Configure port B to enable SPIMISO, SPIMOSI, and SPICLK. Set PBPAR[28, 29,30] and
PBDIR[28, 29, 30], then clear PBODR[28, 29, 30].
For multimaster operation, connect the internal SPISEL input to the SPI by setting PBPAR[31] and
PBDIR[31] and by clearing PBODR[31].
2. Configure a parallel I/O signal to operate as the SPI select output signal if needed. If PB156 is
chosen, clear PBODR[156] and PBPAR[156] and set PBDIR[156].
Freescale Semiconductor
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Serial Peripheral Interface (SPI)
30-15