Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 422

Clocks and Power Control
Input
Frequency
PDF
(MHz) (f )
ref
10 0
10 0
10 0
10 0
10 0
10 0
10 0
45 3
45 2
50 2
50 1
66 2
66 2
1
For MFN = 0, EXTCLK will be synchronized to CLKOUT.
2
Assuming DFNH = 0 and CSR = 0.
The OSCLK can be supplied by either a crystal or an external clock oscillator. Crystals are typically much
cheaper than clock oscillators; however, a clock oscillator has significant design advantages over a crystal
circuit in that clock oscillators are easier to work with, resulting in faster design, debugging, and
production.
14.2.3 DPLL Reset Configuration
While PORESET is asserted, the reset configuration of the DPLL is sampled on the MODCK[1:2] pins.
The DPLL immediately begins to use the multiplication factor and pre-division factor values and external
clock source for OSCLK determined by the sampled MODCK[1:2] pin and attempts to achieve lock;
therefore, the MODCK[1:2] signals should be maintained steadily throughout PORESET assertion. The
mode selection field and various factors are set as shown in
MODCK[1:2] values are internally latched, and the signals applied to MODCK[1:2] can be changed.
14-6
Table 14-2. Typical System Frequency Generation
1
MFI MFN MFD
8 0 0
9 6 9
10 4 9
13 2 9
15 0 0
10 0 0
13 3 9
8 0 0
8 1 2
9 0 0
5 2 6
6 0 1
6 0 1
MPC885 PowerQUICC Family Reference Manual, Rev. 2
PLPRCR
dpgdck S[10:11] JDBCK
160 1
192 1
208 1
264 1
300 1
200 0
266 0
180 1
250 0
300 1
264 0
264 1
264 0
Table 14-3. After PORESET is negated, the
General System
Frequency
2
(MHz) [GCLK2]
80 40
96 48
104 52
132 66
150 75
200 100
266 133
90 45
250 125
150 75
264 132
132 66
264 132
Freescale Semiconductor