Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 604

SDMA Channels and IDMA Emulation
• Single-address memory-write/peripheral-read—The source device is controlled by the IDMA
handshake signals (DREQ and SDACK). When the source device requests service from the IDMA
channel, IDMA asserts SDACK to allow the source device to drive data onto the data bus. The data
is written to the memory address in DAPR, the address type in DFCR, and the size in DCMR. The
data bus is three-stated for this write cycle. The DAPR is incremented by 1, 2, or 4, according to
the programming of DCMR[SIZE]. See
SDACK," for more on IDMA handshake signals.
T3
CLKOUT
Address
TS
R/W
Data
TA
SDACK
19.3.9 External Recognition of an IDMA Transfer
The following are ways to externally determine if IDMA is executing a bus cycle:
• Monitor the AT signals of the SDMA channels for the user-defined function code. (AT0 is always
high for a DMA access.)
• Monitor SDACK, which shows accesses to the peripheral. SDACK activates on either the source
or destination bus cycles, depending on DCMR[S/D]. Note that if Ethernet is running, this method
does not work since SCCs in Ethernet mode also toggle SDACK for SDMA transfers.
19.3.10 Interrupts During an IDMA Bus Transfer
The MPC885 supports a synchronous bus structure with provisions allowing a bus master to detect and
respond to errors during a bus cycle. An IDMA channel recognizes the same bus interrupt sources that the
core recognizes—reset and transfer error acknowledge (TEA).
• Reset—On an external reset, an IDMA immediately aborts channel operation, returns to the idle
state, and clears the IDSR. If a bus cycle is in progress, the cycle is terminated, the control and
19-18
Section 19.3.7, "IDMA Interface Signals—DREQ and
T1 T3 T1 T3
T
DELAY
Figure 19-12. SDACK Timing Diagram: Single-Address
Peripheral Read, Internally Generated TA
MPC885 PowerQUICC Family Reference Manual, Rev. 2
T1 T3 T1 T3
T
HOLD
T1 T3
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