Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 358

External Signals
Table 12-2. MPC875/MPC870 Signal Descriptions (continued)
Hard
Name
Reset
BR Hi-Z
BG Hi-Z
BB Hi-Z
FRZ See
IRQ6 Table 12-3
IRQ0 Hi-Z
IRQ1 Hi-Z
IRQ7 Hi-Z
CS[0:5] High
CS6 High
CE1_B
CS7 High
CE2_B
12-28
Number Type
B11 Bidirectional Bus Request—Asserted low when a possible master is requesting
ownership of the bus. When the MPC875 is configured to work
with the internal arbiter, this signal is configured as an input. When
the MPC875 is configured to work with an external arbiter, this
signal is configured as an output.
D10 Bidirectional Bus Grant—Asserted low when the arbiter of the external bus
grants the bus to a specific device. When the MPC875 is
configured to work with the internal arbiter, BG is configured as an
output and asserted every time the external master asserts BR
and its priority request is higher than any internal sources
requiring a bus transfer. However, when the MPC875 is configured
to work with an external arbiter, BG is an input.
C10 Bidirectional Bus Busy—Asserted low by a master to show that it owns the bus.
active The MPC875 asserts BB after the arbiter grants it bus ownership
pull-up and BB is negated.
B10 Bidirectional Freeze—Output asserted to indicate that the core is in debug
mode.
Interrupt Out 6—One of eight external inputs that can request (by
means of the internal interrupt controller) a service routine from
the core.
M6 Input Interrupt Out 0—One of eight external inputs that can request (by
means of the internal interrupt controller) a service routine from
the core.
P5 Input Interrupt Out 1—One of eight external inputs that can request (by
means of the internal interrupt controller) a service routine from
the core.
N5 Input Interrupt Out 7—One of eight external inputs that can request (by
means of the internal interrupt controller) a service routine from
the core.
B14, E11, Output Chip Select—These outputs enable peripheral or memory devices
C14, B15, at programmed addresses if they are appropriately defined. CS0
E13, B16 can be configured to be the global chip-select for the boot device.
F12 Output Chip Select 6—This output enables a peripheral or memory
device at a programmed address if defined appropriately in the
BR6 and OR6 in the memory controller.
Card Enable 1 Slot B—This output enables even byte transfers
when accesses to the PCMCIA slot B are handled under the
control of the PCMCIA interface.
D15 Output Chip Select 7—This output enables a peripheral or memory
device at a programmed address if defined appropriately in the
BR7 and OR7 in the memory controller.
Card Enable 2 Slot B—This output enables odd byte transfers
when accesses to the PCMCIA slot B are handled under the
control of the PCMCIA interface.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Freescale Semiconductor