Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 648

Serial Communications Controllers
Each Rx and Tx internal clock can be programmed with either an external or internal source. Internal
clocks originate from one of four baud rate generators (BRGs) or one of eight external clock pins; see
Section 20.2.4.3, "SI Clock Route Register (SICR),"
can be as fast as a 1:2 ratio of the system clock. (For example, an SCC internal clock can run at 12.5 MHz
in a 25-MHz system.) However, an SCC's ability to support a sustained bit stream depends on the protocol
as well as other factors. See Appendix B, "Serial Communications Performance."
Associated with each SCC is a digital phase-locked loop (DPLL) for external clock recovery, which
supports NRZ, NRZI, FM0, FM1, Manchester, and Differential Manchester. If the clock recovery function
is not required (that is, synchronous communication), then the DPLL can be disabled, in which case only
NRZ and NRZI are supported.
An SCC can be connected to its own set of pins on the MPC885. This configuration is called the
non-multiplexed serial interface (NMSI) and is described in
an SCC can support standard modem interface signals, RTS, CTS, and CD, through the port C pins and
the CPM interrupt controller (CPIC). If required, software and additional parallel I/O lines can be used to
support additional handshake signals.
Modem Lines
RXD Decoder
21.1 Features
The following is a list of the main SCC features. (Performance figures assume a 25-MHz system clock.)
• Implements HDLC/SDLC, HDLC bus, asynchronous HDLC, BISYNC, synchronous start/stop,
asynchronous start/stop (UART), AppleTalk/LocalTalk, and totally transparent protocols
• Supports 10-Mbps Ethernet/IEEE 802.3 (half- or full-duplex)
• Additional protocols can be added in the future through the use of RAM microcodes.
21-2
Figure 21-1 shows the SCC block diagram.
U-Bus
Control
Registers
Peripheral Bus
Rx
Data
Rx
FIFO
Control
Unit
Delimiter Shifter
Figure 21-1. SCC Block Diagram
MPC885 PowerQUICC Family Reference Manual, Rev. 2
for each SCC's available clock sources. These clocks
Chapter 20, "Serial Interface."
DPLL
and Clock
Recovery
Clock
Generator
Internal Clocks
Tx
Data
Tx
FIFO
Control
Unit
Shifter Delimiter
Using NMSI,
TCLK
RCLK
Modem Lines
Encoder TXD
Freescale Semiconductor