Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 643

Figure 20-29 shows a baud rate generator.
EXTC
CLK2 Pin
Clock
CLK6 Pin
Source
MUX
BRGCLK
Autobaud
RXD n
Control
The BRG clock source can be BRGCLK, CLK2, or CLK6 (selected in BRGCn[EXTC]). The BRGCLK
is generated in the MPC885 clock synthesizer specifically for the BRGs, the SPI, and the I
rate generator. Alternatively, the CLK2 and CLK6 pins can be configured as clock sources. These external
source options allow flexible baud rate frequency generation, independent of the system frequency.
Additionally, CLK2 and CLK6 allow a single external frequency to be the source for multiple BRGs. Note
that the CLK2 and CLK6 signals are not synchronized internally before being used by the BRG.
The BRG provides a divide-by-16 option (BRGCn[DIV16]) and a 12-bit prescaler (BRGCn[CD]) to
divide the source clock frequency. The combined source-clock divide factor can be changed on the fly;
however, two changes should not occur within two source clock periods.
The prescaler output is sent internally to the bank of clocks and can also be output externally on BRGOn
through either the port A or port B parallel I/O. If the BRG divides the clock by an even value, the
transitions of BRGOn always occur on the falling edge of the source clock. If the divide factor is odd, the
transitions alternate between the falling and rising edges of the source clock. Additionally, the output of
the BRG can be sent to the autobaud control block.
Baud Rate Generator Configuration Registers (BRGC n )
20.4.1
Each baud rate generator configuration register (BRGC), shown in
disables the BRG and drives the BRGO output clock high. The BRGC can be written at any time with no
need to disable the SCCs or external devices that are connected to BRGO. Configuration changes occur at
the end of the next BRG clock cycle (no spikes occur on the BRGO output clock). BRGC can be changed
on the fly; however, two changes should not occur within a time equal to two source clock periods.
Freescale Semiconductor
DIV 16
Divide by
1 or 16
ATB
Figure 20-29. Baud Rate Generator (BRG) Block Diagram
MPC885 PowerQUICC Family Reference Manual, Rev. 2
CD[0–11]
Prescaler
BRGOn Clock
12-Bit Counter
1 – 4,096
BRG n
Figure 20-30, is cleared at reset. A reset
Serial Interface
To Pin and/or
Bank of Clocks
2
C internal baud
20-37