Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 737

Electrical pulses between the detector, receiver, and IR receive decoder are nominally the same duration
as those between the IR transmit encoder, output driver, and LED.
Start
Bit
(a) 0
(b)
The SIR encoding/decoding is supported only for SCC2. To activate it, set GSMR_L2[SIR] and configure
GSMR_L2[RDCR, TDCR] for 16x clock operation.
Freescale Semiconductor
UART Frame
Data Bits
1 0 1 0
IR Frame
Figure 25-10. UART and IR Frames
MPC885 PowerQUICC Family Reference Manual, Rev. 2
SCC Asynchronous HDLC Mode and IrDA
0 1 1 0
3/16 Bit Time
Stop
Bit
1
25-15