Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 633

RDM
10 The simplest configuration—each pointer is used continuously and has only one function.
RaPTR points to the active Rxa entry and RbPTR points to the active Rxb entry.
TaPTR points to the active Txa entry and TbPTR points to the active Txb entry.
11 Each pointer is used continuously. The section of SI RAM it points to depends on whether its value is in the first
half (0–15) or the second half (16–31).
• RaPTR points to the active Rxa entry. If RaPTR = 0–15, the current-route RAM is SI RAM address block
0–63 and SISTR[CRORa] = 0. If RaPTR = 16–31, the current-route RAM is SI RAM address block 64–127
and SISTR[CRORa] = 1.
• RbPTR points to the active Rxb entry. If RbPTR = 0–15, the current-route RAM is SI RAM address block
128–191 and SISTR[CRORb] = 0. If RbPTR = 16–31, the current-route RAM is SI RAM address block
192–255 and SISTR[CRORb] = 1.
• RaPTR points to the active Txa entry. If TaPTR = 0–15, the current-route RAM is SI RAM address block
256–319 and SISTR[CROTa] = 0. If TaPTR = 16–31, the current-route RAM is SI RAM address block
320–383 and SISTR[CROTa] = 1.
• TbPTR points to the active Txb entry. If TbPTR = 0–15, the current-route RAM is SI RAM address block
384–447 and SISTR[CROTb] = 0. If TbPTR = 16–31, the current-route RAM is SI RAM address block
448–511 and SISTR[CROTb] = 1.
20.2.5 IDL Bus Implementation
The full-duplex ISDN interchip digital link (IDL) interface connects a physical layer device to the
MPC885. The basic and primary rate of the IDL bus is supported by the MPC885. In the basic rate, data
on three channels (B1, B2, and D) is transferred in a 20-bit frame, providing a full-duplex bandwidth of
160 Kbps. The MPC885 is an IDL slave device that is clocked by the IDL bus master (physical layer
device) and has separate receive and transmit sections. Using both TDMs, the MPC885 supports two
independent IDL buses as shown in
ISDN TE
MPC885
20.2.5.1 ISDN Terminal Adaptor Application
An example IDL application is the ISDN terminal adaptor shown in
the IDL interface connects the 2B+D channels between the MPC885, CODEC, and S/T transceiver. An
SCC is configured in HDLC mode to handle the D channel. Another SCC is used to rate adapt the terminal
Freescale Semiconductor
Table 20-10. SIRP Pointer Values (continued)
Configuration
Figure 20-24.
IDL1
S/T
S/T
Interfaces
IDL2
S/T
Figure 20-24. Dual IDL Bus Application Example
MPC885 PowerQUICC Family Reference Manual, Rev. 2
NT
S/T U
S/T U
Figure 20-25. In such an application,
Serial Interface
U
Interfaces
20-27