Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 233

• A fetch request from the instruction sequencer has priority over burst buffer writes to the cache
array (the burst buffer holds the last missed cache block), thus increasing the overall performance
• The cache efficiently uses the pipeblock of the internal data bus by initiating a new burst cycle (if
miss is detected) while bringing the tail of the previous missed block
• Performance for caching-inhibited regions is enhanced by fetching a full 4-word block into the
burst buffer. Instructions in the burst buffer are only used once before being refetched
7.5.1 Instruction Cache Hit
In the case of a cache hit, the cache block is transferred to the cache block buffer and forwarded to the
stream hit multiplexer and word select multiplexer. As shown in
address select one word of the cache block which is transferred to the instruction sequencer in the core.
7.5.2 Instruction Cache Miss
On an instruction cache miss, the address of the missed instruction is driven on the internal bus with a
4-word burst transfer read request. The transfer begins with the word requested by the instruction
sequencer (critical-word first), followed by the remaining words (if any) of the cache block, then by any
remaining words at the beginning of the block (wrap-around).
On a cache miss, the critical word is simultaneously written to the burst buffer and forwarded to the
instruction sequencer, thus minimizing stalls due to cache fill latency. As subsequent words are received
from the internal bus, they are also written into the burst buffer and delivered to the instruction sequencer
either directly from the internal bus or from the burst buffer (a stream hit). A cache block in the array is
then selected to receive the cache block being gathered in the burst buffer. The selection algorithm gives
first priority to invalid blocks. If all blocks in the set are marked invalid, the block in way 0 is selected. If
none of the blocks in the selected set are invalid, the least recently used block is selected for replacement.
Locked cache blocks are never replaced.
The instruction cache is not blocked to internal accesses while the fetch (caused by a cache miss)
completes. This functionality is sometimes called 'hits under misses,' because the cache can service a hit
while a cache miss fill is waiting to complete. If no bus errors are encountered during the 4-word cache
block fetch, the burst buffer is marked valid and written to the cache array, provided the cache array is not
busy servicing a hit.
If a bus error is encountered while fetching the requested instruction (the critical word), a machine check
exception is generated. If a bus error occurs while fetching subsequent words in the cache block, the burst
buffer is marked invalid and the cache block is not written to the cache array.
7.5.3 Instruction Fetching on a Predicted Path
The core implements branch prediction to allow branches to issue as early as possible. This mechanism
allows instruction prefetching to continue while an unresolved branch is being computed and the condition
is being evaluated. Instructions fetched after unresolved branches are said to be fetched on a predicted
path. These instructions may be discarded later if it turns out that the machine has followed the wrong path.
To minimize power consumption, the MPC885 instruction cache does not initiate a miss sequence in most
Freescale Semiconductor
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Instruction and Data Caches
Figure 7-2, bits 28–29 of the instruction
7-21