Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 888

2
I C Controller
2
32.4.1 I C Mode Register (I2MOD)
2
The I C mode register, shown in
0
Field —
Reset
R/W
Addr
This register is affected by HRESET and SRESET.
Bits Name
0–1 — Reserved and should be cleared.
2 REVD Reverse data. Determines the Rx and Tx character bit order.
0 Normal operation. The msb (bit 0) of each character is sent and received first.
1 Reverse data. The lsb (bit 7) of each character is sent and received first.
Note: Clearing REVD is strongly recommended to ensure consistent bit ordering across devices.
3 GCD General call disable. Determines whether the receiver acknowledges a general call address (all
zeros).
0 General call address is enabled.
1 General call address is disabled.
4 FLT Clock filter. Determines if the I
0 SCL is not filtered.
1 SCL is filtered by a digital filter.
5–6 PDIV Predivider. Selects the clock division factor before it is input into the I
2
the I C BRG is the BRGCLK generated by the SIU.
00 BRGCLK/32
01 BRGCLK/16
10 BRGCLK/8
11 BRGCLK/4
Note: To both save power and reduce noise susceptibility, select the PDIV with the largest division
factor (slowest clock) that still meets performance requirements.
7 EN Enable I
2
0 I C is disabled. The I
2
1 I C is enabled. Do not change other I2MOD bits when EN is set.
32-6
Figure 32-6, controls the I
1 2 3
REVD GCD
2
Figure 32-6. I C Mode Register (I2MOD)
Table 32-1. I2MOD Field Descriptions
2
C input clock SCL is filtered to prevent spikes in a noisy environment.
2
C operation.
2
C is in a reset state and consumes minimal power.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
2
C modes and clock source.
4 5
FLT
0000_0000
R/W
0x860
Table 32-1 describes I2MOD bit functions.
Description
6 7
PDIV EN
2
C BRG. The clock source for
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