Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 51

Figure
Number
10-18 Decrementer Register (DEC) .............................................................................................. 10-22
10-19 Timebase Upper Register (TBU) ........................................................................................ 10-23
10-20 Timebase Lower Register (TBL) ........................................................................................ 10-24
10-21 Timebase Reference Registers (TBREFA and TBREFB)................................................... 10-24
10-22 Timebase Status and Control Register (TBSCR) ................................................................ 10-25
10-23 Periodic Interrupt Timer Block Diagram ............................................................................ 10-26
10-24 Periodic Interrupt Status and Control Register (PISCR)..................................................... 10-26
10-25 PIT Count Register (PITC) ................................................................................................. 10-27
10-26 PIT Register (PITR) ............................................................................................................ 10-28
11-1 Power-On and Hard Reset Sequence .................................................................................... 11-3
11-2 Soft Reset Sequence.............................................................................................................. 11-4
11-3 Reset Status Register (RSR).................................................................................................. 11-5
11-4 Data Bus Configuration Input Circuit ................................................................................... 11-6
11-5 Reset Configuration Sampling for Short PORESET Assertion............................................ 11-7
11-6 Reset Configuration Sampling for Long PORESET Assertion ............................................ 11-7
11-7 Reset Configuration Sampling Timing Requirements .......................................................... 11-8
11-8 Hard Reset Configuration Word............................................................................................ 11-8
12-1 MPC885 Signals and Pin Numbers (Part 1).......................................................................... 12-2
12-2 MPC885 Signals and Pin Numbers (Part 2).......................................................................... 12-3
12-3 MPC875 Signals and Pin Numbers (Part 1)........................................................................ 12-24
12-4 MPC875 Signals and Pin Numbers (Part 2)........................................................................ 12-25
12-5 Three-State Buffers and Active Pull-Up Buffers ................................................................ 12-41
13-1 Input Sample Window........................................................................................................... 13-2
13-2 MPC885 Bus Signals ............................................................................................................ 13-3
13-3 Basic Transfer Protocol......................................................................................................... 13-6
13-4 Basic Flow Diagram of a Single-Beat Read Cycle ............................................................... 13-7
13-5 Basic Timing: Single-Beat Read Cycle, Zero Wait States .................................................... 13-8
13-6 Basic Timing: Single-Beat Read Cycle, One Wait State....................................................... 13-9
13-7 Basic Flow of a Single-Beat Write Cycle ........................................................................... 13-10
13-8 Basic Timing: Single-Beat Write Cycle, Zero Wait States ................................................. 13-11
13-9 Basic Timing: Single-Beat Write Cycle, One Wait State.................................................... 13-12
13-10 Basic Timing: Single-Beat, 32-Bit Data Write Cycle, 16-Bit Port Size ............................. 13-13
13-11 Basic Flow of a Burst-Read Cycle...................................................................................... 13-16
13-12 Burst-Read Cycle: 32-Bit Port Size, Zero Wait State ......................................................... 13-17
13-13 Burst-Read Cycle: 32-Bit Port Size, One Wait State .......................................................... 13-18
13-14 Burst-Read Cycle: 32-Bit Port Size, Wait States between Beats ........................................ 13-19
13-15 Burst-Read Cycle: 16-Bit Port Size, One Wait State between Beats .................................. 13-20
13-16 Basic Flow of a Burst Write Cycle...................................................................................... 13-21
13-17 Burst-Write Cycle: 32-Bit Port Size, Zero Wait States ....................................................... 13-22
13-18 Burst-Inhibit Cycle: 32-Bit Port Size.................................................................................. 13-23
13-19 Internal Operand Representation ........................................................................................ 13-24
Freescale Semiconductor
Figures
Title
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Page
Number
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