Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 804

Powerquicc family

Table of Contents

Serial Management Controllers (SMCs)

Ability to transmit data on demand using the TODR

SCCS register to determine idle status of the receive pin

Other features for the SCCs as described in the GSMR

However, the SMC UART frame format, shown in

SCC format supports only up to 8 bits.

1. Clock is not to scale.

SMC UART Features

The following list summarizes the main features of the SMC in UART mode:

Flexible message-oriented data structure

Programmable data length (5–14 bits)

Programmable 1 or 2 stop bits

Even/odd/no parity generation and checking

Frame error, break, and IDLE detection

Transmit preamble and break sequences

Received break character length indication

Continuous receive and transmit modes

SMC UART-Specific Parameter RAM

For UART mode, the protocol-specific area of the SMC parameter RAM is mapped as in

Table 29-4. SMC UART-Specific Parameter RAM Memory Map

MAX_IDL Hword Maximum idle characters. When a character is received on the line, the SMC starts counting

Hword Temporary idle counter. Down-counter in which the CP stores the current idle counter value

5 to 14 Data Bits with the

Least Significant Bit First

Figure 29-5. SMC UART Frame Format

idle characters received. If MAX_IDL idle characters arrive before the next character, an idle

time-out occurs and the buffer closes, which sends an interrupt request to the core to receive

data from the buffer. An idle character is defined as a full character length of logic high.

MAX_IDL can be used to demarcate frames in UART mode. Clearing MAX_IDL disables this

function so idle never causes the buffer to close, regardless of how many idle characters are

received. The length of an idle character is calculated as follows: 1 + data length (5 to 14) + 1

(if parity bit is used) + number of stop bits (1 or 2). For example, for 8 data bits, no parity, and

1 stop bit, character length is 10 bits.

in the MAX_IDL time-out process.

MPC885 PowerQUICC Family Reference Manual, Rev. 2

29-5, allows a data length of up to 14 bits. The

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