Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 562

Communications Processor Module and CPM Timers
17.2.3.1 Timer Global Configuration Register (TGCR)
The timer global configuration register (TGCR) contains configuration parameters used by all four timers.
It allows simultaneous starting and stopping of any number of timers as long as one bus cycle is used to
access TGCR.
0 1 2
Field CAS4 FRZ4 STP4 RST4 GM2 FRZ3 STP3 RST3 CAS2 FRZ2 STP2 RST2 GM1 FRZ1 STP1 RST1
Reset
R/W
Addr
This register is affected by HRESET and SRESET.
Bits Name
0 CAS4 Cascade timers
0 Normal operation
1 Timers 3 and 4 are cascaded to form a 32-bit timer.
FRZ x Freeze timer x
1, 5, 9,
13 0 The corresponding timer ignores the FRZ state.
1 Stops the corresponding timer if the MPC885 enters FRZ state. FRZ state is entered in debug
mode as defined in
STP x Stop timer x
2, 6,
10, 14 0 Normal operation
1 Stop the timer. This bit stops all clocks to the timer, except the U-bus interface clock allowing the
timer registers to be read or written. The clocks to the timer remain inactive until this bit is cleared
or a hardware reset occurs.
3, 7, RST x Reset timer x
11, 15 The associated TMR x and TRR x registers should be initialized before enabling the timer with RST x .
0 Reset the corresponding timer. Upon clearing this bit, all associated timer registers are reset.
1 Enable the corresponding timer if STP is cleared.
4 GM2 Gate mode for TGATE2. Valid only if TMR3[GE] or TMR4[GE] is set.
0 Restart gate mode. A falling edge of TGATE2 enables and restarts the count and a rising edge of
TGATE2 disables the count.
1 Normal gate mode. This mode is the same as 0, except the falling edge of TGATE2 does not restart
the count value in the TCN.
8 CAS2 Cascade timers
0 Normal operation
1 Timers 1 and 2 are cascaded to form a 32-bit timer.
12 GM1 Gate mode for TGATE1. Valid only if TMR1[GE] or TMR2[GE] is set.
0 Restart gate mode. A falling TGATE1 enables and restarts the count and a rising edge of TGATE1
disables the count.
1 Normal gate mode. This mode is the same as 0, except the falling edge of TGATE1 does not restart
the count value in the TCN.
17-8
3 4 5 6
Figure 17-5. Timer Global Configuration Register (TGCR)
Table 17-1. TGCR Field Descriptions
Chapter 53, "System Development and Debugging."
MPC885 PowerQUICC Family Reference Manual, Rev. 2
7 8 9 10 11
0
R/W
0x980
Table 17-1 describes the TGCR fields.
Description
12 13 14 15
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