Overflow And Underflow; Instruction Descriptions - Freescale Semiconductor PowerPC e500 Core Reference Manual

Auxiliary Processing Units (APUs)

10.4.2.3 Overflow and Underflow

Defining pmax to be the most positive normalized value (farthest from zero), pmin the smallest
positive normalized value (closest to zero), nmax the most negative normalized value (farthest
from zero) and nmin the smallest normalized negative value (closest to zero), an overflow is said
to have occurred if the numerically correct result of an instruction is such that r>pmax or r<nmax.
Additionally, an implementation may also signal overflow by comparing the exponents of the
operands. In this case, the hardware examines both exponents ignoring the fractional values. If it
is determined that the operation to be performed may overflow (ignoring the fractional values), an
overflow may be said to occur. For addition and subtraction this can occur if the larger exponent
of both operands is 2046 for double-precision. For multiplication this can occur if the sum of the
exponents of the operands less the bias is 2046 for double-precision. Thus:
double-precision addition:
if A
double-precision multiplication:
if A
An underflow is said to have occurred if the numerically correct result of an instruction is such that
0<r<pmin or nmin<r<0. In this case, r may be denormalized, or may be smaller than the smallest
denormalized number. As with overflow detection, an implementation may also signal underflow
by comparing the exponents of the operands. In this case, the hardware examines both exponents
regardless of the fractional values. If it is determined that the operation to be performed may
underflow (ignoring the fractional values), an underflow may be said to occur. For division this can
occur if the difference of the exponent of the A operand less the exponent of the B operand less
the bias is 1. Thus:
double-precision multiplication:
if A

10.4.3 Instruction Descriptions

This section describes double-precision floating-point computational and logical instructions. The
following load and store instructions defined by the SPE APU are used to load and store operands:
• evldd—Vector Load Double Word into Double Word
• evlddx—Vector Load Double Word into Double Word Indexed
• evstdd—Vector Store Double Word of Double Word
• evstddx—Vector Store Double Word of Double Word
• evmergehi—Vector Merge High
• evmergelo—Vector Merge Low
These instruction descriptions follow the conventions used in the EREF.
10-6
>= 2046 | B
exp exp
+ B - 1023 >= 2046 then overflow
exp exp
- B - 1023 <= 1 then underflow
exp exp
PowerPC e500 Core Family Reference Manual, Rev. 1
>= 2046 then overflow
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