Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 163

Table 4-6 lists supervisor-level SPRs defined by the PowerPC architecture.
SPR Number
Decimal SPR[5–9]
18 00000
19 00000
22 00000
26 00000
27 00000
272 01000
273 01000
274 01000
275 01000
284 01000
285 01000
287 01000
1
Any read (mftb) to this address causes an implementation-dependent software emulation exception.
4.1.2.1 DAR, DSISR, and BAR Operation
The LSU updates the DAR, DSISR, and BAR when an exception is taken.
• When a bus error occurs, the data address register (DAR) is loaded with the effective address. For
instructions that generate multiple accesses, the effective address of the first offending tenure is
loaded.
• The DSI status register (DSISR) notifies the error handler when an exception is caused by a load
or store. For a data MMU error, the data MMU loads the DSISR with error status. For alignment
exceptions, the DSISR is loaded with the instruction information as defined by the PowerPC
architecture.
• The breakpoint address register (BAR) notifies the address on which a data breakpoint occurred.
For a multiple-cycle instruction, the BAR contains the address of the first cycle with which the
breakpoint condition was associated. The BAR has a valid value only when a data breakpoint
exception is taken. At any other time, its value is boundedly undefined. (This term is defined very
Freescale Semiconductor
Table 4-6. Supervisor-Level PowerPC SPRs
Name
SPR[0–4]
10010 DSISR See the Programming Environments
Manual and
DSISR, and BAR Operation."
10011 DAR See the Programming Environments
Manual and
DSISR, and BAR Operation."
10110 DEC See
Register (DEC),"
and Power Control."
11010 SRR0 See SRR0 settings for individual
exceptions in
11011 SRR1 See SRR1 settings for individual
exceptions in
10000 SPRG0 See the Programming Environments
Manual .
10001 SPRG1
10010 SPRG2
10011 SPRG3
1
11100 TBL write See
Chapter 14, "Clocks and Power Control."
1
11101 TBU write
11111 PVR Section 4.1.2.3.2, "Processor Version
Register."
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Reference/Section
Section 4.1.2.1, "DAR,
Section 4.1.2.1, "DAR,
Section 10.8.1, "Decrementer
and Chapter 14, "Clocks
Chapter 6, "Exceptions."
Chapter 6, "Exceptions."
Section 10.9, "Timebase," and
MPC8xx Core Register Set
Serialize Access
Write: Full sync
Read: Sync relative to
load/store operations
Write: Full sync
Read: Sync relative to
load/store operations
Write
Write
Write
Write
Write (as a store)
No (read-only register)
4-5