Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 840

Serial Peripheral Interface (SPI)
30.5 SPI Parameter RAM
The SPI parameter RAM area begins at the SPI base address. It is similar to the SCC general-purpose
parameter RAM. Some values must be user-initialized before the SPI is enabled; the CPM initializes the
others. Once initialized, parameter RAM values do not usually need to be accessed. They should be
changed only when the SPI is inactive.
1
Offset Name Width
0x00 RBASE Hword Rx/Tx BD table base address. Indicate where the BD tables begin in the dual-port RAM.
0x02 TBASE Hword
0x04 RFCR Byte
0x05 TFCR Byte
0x06 MRBLR Hword Maximum receive buffer length. The SPI has one MRBLR entry to define the maximum
0x08 RSTATE Word Rx internal state. Reserved for CPM use.
0x0C — Word The Rx internal data pointer
0x10 RBPTR Hword RxBD pointer. Points to the current Rx BD being processed or to the next BD to be
0x12 — Hword The Rx internal byte count
0x14 — Word Rx temp. Reserved for CPM use.
0x18 TSTATE Word Tx internal state. Reserved for CPM use.
0x1C — Word The Tx internal data pointer
0x20 TBPTR Hword TxBD pointer. Points to the current Tx BD during frame transmission or the next BD to be
0x22 — Hword The Tx internal byte count
30-10
Table 30-5 shows the memory map of the SPI parameter RAM.
Table 30-5. SPI Parameter RAM Memory Map
Setting Rx/TxBD[W] in the last BD in each BD table determines how many BDs are
allocated for the Tx and Rx sections of the SPI. Initialize RBASE/TBASE before enabling
the SPI. Furthermore, do not configure BD tables of the SPI to overlap any other active
controller's parameter RAM.
RBASE and TBASE should be divisible by eight.
Rx/Tx function code. Contains the value to appear on AT[1-3] when the associated SDMA
channel accesses memory. Also controls byte ordering for the transfers. See
Section 30.5.1, "Receive/Transmit Function Code Registers (RFCR/TFCR)."
number of bytes the MPC885 writes to a Rx buffer before moving to the next buffer. The
MPC885 can write fewer bytes than MRBLR if an error or end-of-frame occurs, but never
exceeds the MRBLR value. User-supplied buffers should be no smaller than MRBLR.
Tx buffers are unaffected by MRBLR and can have varying lengths; the number of bytes
to be sent is programmed in TxBD[Data Length].
MRBLR is not intended to be changed while the SPI is operating. However it can be
changed in a single bus cycle with one 16-bit move (not two 8-bit bus cycles
back-to-back). The change takes effect when the CPM moves control to the next RxBD.
To guarantee the exact RxBD on which the change occurs, change MRBLR only while
the SPI receiver is disabled. MRBLR should be greater than zero; it should be an even
number if the character length of the data exceeds 8 bits.
2
in the buffer to be accessed.
serviced when idle. After a reset or when the end of the BD table is reached, the CPM
initializes RBPTR to the RBASE value. Most applications should not modify RBPTR, but
it can be updated when the receiver is disabled or when no Rx buffer is in use.
2
is a down-count value that is initialized with the MRBLR value
and decremented with every byte the SDMA channels write.
2
is updated by the SDMA channels to show the next address
in the buffer to be accessed.
processed when idle. After reset or when the end of the Tx BD table is reached, the CPM
initializes TBPTR to the TBASE value. Most applications do not need to modify TBPTR,
but it can be updated when the transmitter is disabled or when no Tx buffer is in use.
2
is a down-count value initialized with TxBD[Data Length]and
decremented with every byte read by the SDMA channels.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
is updated by the SDMA channels to show the next address
Freescale Semiconductor