Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 746

SCC BISYNC Mode
Table 26-5 describes BSYNC fields.
Bits Name
0 V Valid. If V = 1 and the receiver is not in hunt mode when a SYNC character is received, this character
is discarded.
1–7 — All zeros
8–15 SYNC SYNC character
26.8 SCC BISYNC DLE Register (BDLE)
The BDLE register is used to define the BISYNC stripping and insertion of DLE characters. When an
underrun occurs while a message is being sent in transparent mode, the BISYNC controller inserts
DLE-SYNC pairs until the next buffer is available for transmission.
In transparent mode, the receiver discards any DLE character received and excludes it from the BCS if the
valid bit (BDLE[V]) is set. If the second character is SYNC, the controller discards it and excludes it from
the BCS. If it is a DLE, the controller writes it to the buffer and includes it in the BCS. If it is not a DLE
or SYNC, the controller examines the control character table and acts accordingly. If the character is not
in the table, the buffer is closed with the DLE follow character error bit set. If the valid bit is not set, the
receiver treats the character as a normal character. When using 7-bit characters with parity, the parity bit
should be included in the DLE register value.
0 1
Field V 0
Reset
R/W
Addr
Table 26-6 describes BDLE fields.
Bits Name
0 V Valid. If V = 1 and the receiver is not in hunt mode when a SYNC character is received, this character
is discarded.
1–7 — All zeros
8–15 DLE DLE character
26.9 Sending and Receiving the Synchronization Sequence
The BISYNC channel can be programmed to send and receive a synchronization pattern defined in the
DSR. GSMR_H[SYNL] defines pattern length, as shown in
26-8
Table 26-5. BSYNC Field Descriptions
2 3 4 5 6
0 0 0 0 0
SCC Base + 0x40
Figure 26-4. BISYNC DLE (BDLE)
Table 26-6. BDLE Field Descriptions
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
7 8
0
Undefined
R/W
Description
Table 26-7. The receiver synchronizes on this
15
DLE
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