Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 686

SCC UART Mode
Bit Name
2–3 CL Character length. Determines the number of data bits in the character, not including optional parity
or multidrop address bits. If a character is less than 8 bits, most-significant bits are received as zeros
and are ignored when the character is sent. CL can be modified on the fly.
00 5 data bits
01 6 data bits
10 7 data bits
11 8 data bits
4–5 UM UART mode. Selects the asynchronous channel protocol. UM can be modified on the fly.
00 Normal UART operation. Multidrop mode is disabled and idle-line wake-up mode is selected.
The UART receiver leaves hunt mode by receiving an idle character (all ones).
01 Manual multidrop mode. An additional address/data bit is sent with each character. Multidrop
asynchronous modes are compatible with the MC68681 DUART, MC68HC11 SCI, DSP56000
SCI, and Intel 8051 serial interface. The receiver leaves hunt mode when the address/data bit is
a one, indicating the received character is an address that all inactive processors must process.
The controller receives the address character and writes it to a new buffer. The core then
compares the written address with its own address and decides whether to ignore or process
subsequent characters.
10 Reserved
11 Automatic multidrop mode. The CPM compares the address of an incoming address character
with UADDR x parameter RAM values; subsequent data is accepted only if a match occurs.
6 FRZ Freeze transmission. Allows the UART transmitter to pause and later continue from that point.
0 Normal operation. If the buffer was previously frozen, it resumes transmission from the next
character in the same buffer that was frozen.
1 The SCC completes transmission of any data already transferred to the Tx FIFO (the number of
characters depends on GSMR_H[TFL]) and then freezes. After FRZ is cleared, transmission
resumes from the next character.
7 RZS Receive zero stop bits
0 The receiver operates normally, but at least one stop bit is needed between characters. A framing
error is issued if a stop bit is missing. Break status is set if an all-zero character is received with
a zero stop bit.
1 Configures the receiver to receive data without stop bits. Useful in V.14 applications where SCC
UART controller data is supplied synchronously and all stop bits of a particular character can be
omitted for cross-network rate adaptation. RZS should be set only if SYN is set. The receiver
continues if a stop bit is missing. If the stop bit is a zero, the next bit is considered the first data
bit of the next character. A framing error is issued if a stop bit is missing, but a break status is
reported only after two consecutive break characters have no stop bits.
8 SYN Synchronous mode
0 Normal asynchronous operation. GSMR_L[TENC,RENC] must select NRZ and GSMR_L[TDCR,
RDCR] select either 8×, 16×, or 32×. 16× is recommended for most applications.
1 Synchronous SCC UART controller using 1× clock (isochronous UART operation).
GSMR_L[TENC, RENC] must select NRZ and GSMR_L[RDCR, TDCR] select 1× mode. A bit is
transferred with each clock and is synchronous to the clock, which can be internal or external.
9 DRT Disable receiver while transmitting
0 Normal operation
1 While the SCC is sending data, the internal RTS disables and gates the receiver. Useful for a
multidrop configuration in which the user does not want to receive its own transmission. For
multidrop UART mode, set the BDs' preamble bit, TxBD[P].
10 — Reserved, should be cleared.
22-14
Table 22-9. PSMR UART Field Descriptions (continued)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Freescale Semiconductor