Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 57

Figure
Number
22-9 SCC UART Transmit Buffer Descriptor (TxBD) ............................................................... 22-18
22-10 SCC UART Interrupt Event Example ................................................................................. 22-20
22-11 SCC UART Event Register (SCCE) and Mask Register (SCCM) ..................................... 22-20
22-12 SCC Status Register for UART Mode (SCCS) ................................................................... 22-22
23-1 HDLC Framing Structure...................................................................................................... 23-2
23-2 HDLC Address Recognition ................................................................................................. 23-4
23-3 HDLC Mode Register (PSMR)............................................................................................. 23-7
23-4 SCC HDLC Receive Buffer Descriptor (RxBD) .................................................................. 23-8
23-5 SCC HDLC Receiving using RxBDs.................................................................................. 23-10
23-6 SCC HDLC Transmit Buffer Descriptor (TxBD) ............................................................... 23-11
23-7 HDLC Event Register (SCCE)/HDLC Mask Register (SCCM) ........................................ 23-12
23-8 SCC HDLC Interrupt Event Example................................................................................. 23-13
23-9 SCC HDLC Status Register (SCCS)................................................................................... 23-14
23-10 Typical HDLC Bus Multimaster Configuration.................................................................. 23-17
23-11 Typical HDLC Bus Single-Master Configuration............................................................... 23-18
23-12 Detecting an HDLC Bus Collision...................................................................................... 23-19
23-13 Nonsymmetrical Tx Clock Duty Cycle for Increased Performance ................................... 23-19
23-14 HDLC Bus Transmission Line Configuration .................................................................... 23-20
23-15 Delayed RTS Mode............................................................................................................. 23-20
23-16 HDLC Bus TDM Transmission Line Configuration .......................................................... 23-21
24-1 LocalTalk Frame Format....................................................................................................... 24-1
24-2 Connecting the MPC885 to LocalTalk.................................................................................. 24-3
25-1 Asynchronous HDLC Frame Structure................................................................................. 25-2
25-2 Receive Flowchart................................................................................................................. 25-3
25-3 TXCTL_TBL/RXCTL_TBL ................................................................................................ 25-5
25-4 Asynchronous HDLC Event Register (SCCE)/Asynchronous HDLC Mask Register (SCCM) ..
25-8
25-5 SCC Status Register for Asynchronous HDLC Mode (SCCS)............................................. 25-9
25-6 Asynchronous HDLC Mode Register (PSMR)................................................................... 25-10
25-7 SCC Asynchronous HDLC RxBDs .................................................................................... 25-11
25-8 SCC Asynchronous HDLC TxBDs..................................................................................... 25-12
25-9 Serial Infrared (SIR) Link ................................................................................................... 25-14
25-10 UART and IR Frames ......................................................................................................... 25-15
26-1 Classes of BISYNC Frames.................................................................................................. 26-1
26-2 Control Character Table and RCCM..................................................................................... 26-6
26-3 BISYNC SYNC (BSYNC) ................................................................................................... 26-7
26-4 BISYNC DLE (BDLE) ......................................................................................................... 26-8
26-5 Protocol-Specific Mode Register for BISYNC (PSMR) .................................................... 26-10
26-6 SCC BISYNC RxBD .......................................................................................................... 26-11
26-7 SCC BISYNC TxBD .......................................................................................................... 26-13
26-8 BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM) ................................. 26-15
Freescale Semiconductor
Figures
Title
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Page
Number
lvii