Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 868

Universal Serial Bus (USB)
31.11.5 USB Event Register (USBER)
The USBER reports events recognized by the USB channel and generates interrupts. Upon recognition of
an event, the USB sets its corresponding bit in the USBER. Interrupts generated by this register may be
masked in the USB mask register.
The USBER may be read at any time. A bit is cleared by writing a one (writing a zero does not affect a
bit's value). More than one bit may be cleared at a time. All unmasked bits must be cleared before the CP
will clear the internal interrupt request. This register is cleared at reset.
0
Field
Reset
R/W
Addr
Table 31-12 describes USBER fields.
Bit Name
0 –5 —
6 RESET
7 IDLE
8–11 TXE x
12 SOF
13 BSY
14 TXB
15 RXB
31.11.6 USB Mask Register (USBMR)
The USBMR is a 16-bit read/write register (0xA14) that has the same bit formats as the USB event register.
If a bit in the USBMR is one, the corresponding interrupt in the USBER is enabled. If the bit is zero, the
corresponding interrupt in the USBER will be masked. This register is cleared at reset.
31-20
5 6
— RESET IDLE TXE4 TXE3 TXE2 TXE1 SOF
0000_0000_0000_0000
Figure 31-16. USB Event Register (USBER)
Table 31-12. USBER Fields
Reserved, should be cleared.
Reset condition detected. USB reset condition was detected asserted.
IDLE status changed. A change in the status of the serial line was detected. The real time
suspend status is reflected in the USB status register.
Tx error. An error occurred during transmission for endpoint x (packet not acknowledged or
underrun).
Start of frame. A start of frame packet was received. The packet is stored in the FRAME_N
parameter RAM entry.
Busy condition. Received data has been discarded due to a lack of buffers. This bit is set
after the first character is received for which there is no receive buffer available.
Tx buffer. A buffer has been transmitted. This bit is set once the transmit data of the last
character in the buffer was written to the transmit FIFO (if L=0 (last bit)) or after the last
character was transmitted on the line (if L=1).
Rx buffer. A buffer has been received. This bit is set after the last character has been written
to the receive buffer and the RxBD is closed.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
7 8 9 10 11
R/W
0xA10
Description
12 13 14 15
BSY TXB RXB
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