Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 193

Chapter 6
Exceptions
Core exceptions can be generated when an exception condition occurs. Exception sources in the MPC885
include the following:
• External interrupt request
• Certain memory access conditions (protection faults and bus errors)
• Internal errors, such as an attempt to execute an unimplemented opcode
• Trap instructions
• Internal exceptions (breakpoints and debug counter's expiration)
Exception handling is transparent to user software and uses the same mechanism to handle all types of
exceptions. When an exception is taken, control is transferred to an exception handler located at an offset
defined for the type of exception encountered. The exception prefix bit, MSR[IP], determines whether this
base address for the vector table resides at 0x000n_nnnn (IP = 0) or 0xFFFn_nnnn (IP = 1). Exceptions
are handled in supervisor mode.
After the exception has been handled, the handler returns control to the interrupting program. As specified
in the Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture, the
core implements a precise exception model. This means that when an exception is taken, the following
conditions are met:
• Subsequent instructions in the program flow are discarded.
• Previous instructions finish and write back their results.
• The address of the faulting instruction is saved in SRR0 and the machine state of the interrupted
process is saved in SRR1.
• When the exception is taken, the instruction causing the exception might not have started
executing, could be partially executed, or has completed, depending on the exception and
instruction types. See
For more information, see
6.1 Exceptions
The OEA defines a set of exceptions for processors which implement the PowerPC architecture, some of
which are optional. The following sections describe exceptions implemented on the MPC885. Those
defined by the OEA are described in
"Implementation-Specific Exceptions,"
All exceptions associated with memory are implemented as precise, which means that a load/store
instruction is not complete until all possible error indications are sampled from the load/store bus. This
also implies that a store or nonspeculative load instruction is not issued to the load/store bus until all
Freescale Semiconductor
Table 6-20.
Section 6.1.4, "Implementing the Precise Exception Model."
Section 6.1.2, "PowerPC-Defined Exceptions." Section 6.1.3,
describes implementation-specific exceptions.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
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