Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 156

The MPC8xx Core
Table 3-4 summarizes MPC885 features with respect to the VEA definition.
Functionality
Memory Memory coherency is not supported in the MPC885 hardware, but can be performed in the software
coherency or by defining memory as cache inhibited. In addition, the MPC885 does not provide any data storage
attributes to an external system.
Atomic update Both the lwarx and stwcx. instructions are implemented according to the PowerPC architecture
primitives requirements. When memory accessed by the lwarx and stwcx. instructions is in the cache-allowed
mode, it is assumed that the system works with the single master in this memory region. Therefore, if
a data cache miss occurs, the access on the internal and external buses does not have a reservation
attribute. The MPC885MPC885 does not cause the system DSI exception handler to be invoked if
memory accessed by the lwarx and stwcx. instructions is in write-through required mode. Also, the
MPC885 does not support snooping an external bus activity outside the chip. The provision is made
to cancel the reservation inside the MPC885 by using the CR and KR input signals. For accesses to
internal resources, internal snoop logic monitors the internal bus for communication processor module
(CPM) accesses of the address associated with the last lwarx instruction.
The effect of The LSU hardware supports all PowerPC integer load/store instructions. Naturally-aligned operands
operand give optimal performance for a maximum size of four bytes. Unaligned operands are supported in
placement on hardware and are broken into a series of aligned transfers. The effect of operand placement on
performance performance is as stated in the VEA, except for 8-byte operands. Because the MPC885 uses a 32-bit
data bus, performance is good rather than optimal. See
description of integer unaligned instruction execution and timing; see
Latency,"
Memory The MPC885 interprets cache control instructions as if they pertain only to the MPC885 cache. These
control instructions do not broadcast. Any bus activity caused by these instructions results from an operation
instructions performed on the MPC885 cache and not because of the instruction itself.
• Instruction Cache Block Invalidate (icbi)—The MMU translates the EA and the associated
instruction cache block is invalidated if hit.
• Instruction Synchronize (isync)—The isync instruction waits for all previous instructions to
complete and discards any prefetched instructions, causing subsequent instructions to be fetched
or refetched from memory and executed.
• Data Cache Block Touch (dcbt) and Data Cache Block Touch for Store (dcbtst)—The appropriate
cache block is checked for a hit. If it is a miss, the instruction is treated as a regular miss, except
that bus error does not cause an exception. If no error occurs, the cache is updated.
• Data Cache Block Set to Zero (dcbz)—Executes as defined in the VEA.
• Data Cache Block Store (dcbst)—Executes as defined in the VEA.
• Data Cache Block Invalidate (dcbi)—The MMU translates the EA and the associative data cache
block is invalidated if hit.
• Data Cache Block Flush (dcbf)—Executes as defined in the VEA.
• Enforce In-Order Execution of I/O (eieio)—When executing an eieio instruction, the LSU waits for
previous accesses to terminate before beginning accesses associated with load/store instructions
after the eieio instruction.
Time base The time base functions as defined by the VEA and supports an additional implementation-specific
exception. The time base is described in
"Clocks and Power Control."
3-16
Table 3-4. VEA-Level Features
for a description of string instruction timing.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Section 3.6.3.5, "Unaligned Accesses,"
Section 9.2.2, "String Instruction
Chapter 10, "System Interface Unit,"
for a
and in Chapter 14,
Freescale Semiconductor