Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 677

Powerquicc family

Table of Contents

Table 22-1. UART-Specific SCC Parameter RAM Memory Map (continued)

From SCC base. SCC base = IMMR + 0x3D00 (SCC2) or 0x3E00 (SCC3) or 0x3F00 (SCC4)

Data-Handling Methods: Character- or Message-Based

An SCC UART controller uses the same BD table and buffer structures as the other protocols and supports

both multibuffer, message-based and single-buffer, character-based operation.

For character-based transfers, each character is sent with stop bits and parity and received into separate

1-byte buffers. A maskable interrupt is generated when each buffer is received.

In a message-based environment, transfers can be made on entire messages rather than on individual

characters. To simplify programming and save processor overhead, a message is transferred as a linked list

of buffers without core intervention. For example, before handling input data, a terminal driver may wait

for an end-of-line character or an idle timeout rather than be interrupted when each character is received.

Conversely, ASCII files can be sent as messages ending with an end-of-line character.

When receiving messages, up to eight control characters can be configured to mark the end of a message

or generate a maskable interrupt without being stored in the buffer. This option is useful when flow control

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Control character 1–8. These characters define the Rx control characters on

which interrupts can be generated.

Receive control character mask. Used to mask comparison of

CHARACTER1–8 so classes of control characters can be defined. A one

enables the comparison, and a zero masks it.

Receive control character register. Used to hold the last rejected control

character (not written to the Rx buffer). Generates a maskable interrupt. If the

core does not process the interrupt and read RCCR before a new control

character arrives, the previous control character is overwritten.

Receive last break character. Used in synchronous UART when PSMR[RZS]

= 1; holds the last break character pattern. By counting zeros in RLBC, the

core can measure break length to a one-bit resolution. Read RLBC by

counting the zeros written from bit 0 to where the first one was written. RLBC

= 0b001xxxxxxxxxxxxx indicates two zeros; 0b1xxxxxxxxxxxxxxx indicates

Note that RLBC can be used in combination with BRKLN above to measure

the break length down to a bit resolution: (BRKLN + number of zeros in

MPC885 PowerQUICC Family Reference Manual, Rev. 2

SCC UART Mode