Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 268

Memory Management Unit
Bits Name
28 SFP Supervisor (supervisor) fetch permission
0 Subpage 0 (Address[20–21] = 00) Supervisor fetch is not permitted
1 Subpage 0 (Address[20–21] = 00) Supervisor fetch is permitted
29 0 Subpage 1 (Address[20–21] = 01) Supervisor fetch is not permitted
1 Subpage 1 (Address[20–21] = 01) Supervisor fetch is permitted
30 0 Subpage 2 (Address[20–21] = 10) Supervisor fetch is not permitted
1 Subpage 2 (Address[20–21] = 10) Supervisor fetch is permitted
31 0 Subpage 3 (Address[20–21] = 11) Supervisor fetch is not permitted
1 Subpage 3 (Address[20–21] = 11) Supervisor fetch is permitted
8.8.12.3 IMMU RAM Entry Read Register 1 (MI_RAM1)
The IMMU RAM entry read register 1 (MI_RAM1), shown in
information of the entry indexed by MI_CTR[ITLB_INDX]. This register is updated only when MI_CAM
is written to
.
0
Field
Reset
R/W
16
Field
Reset
R/W
SPR
Table 8-19 describes MI_RAM1 fields.
Bits Name
0–25 —
26 UFP
27
28
29
8-26
Table 8-18. MI_RAM0 Field Descriptions (continued)
—
0
Figure 8-19. IMMU RAM Entry Read Register 1 (MI_RAM1)
Table 8-19. MI_RAM1 Field Descriptions
Reserved
User fetch permission
0 Subpage 0 (Address[20–21] = 00) User fetch is not permitted
1 Subpage 0 (Address[20–21] = 00) User fetch is permitted
0 Subpage 1 (Address[20–21] = 01) User fetch is not permitted
1 Subpage 1 (Address[20–21] = 01) User fetch is permitted
0 Subpage 2 (Address[20–21] = 10) User fetch is not permitted
1 Subpage 2 (Address[20–21] = 10) User fetch is permitted
0 Subpage 3 (Address[20–21] = 11) User fetch is not permitted
1 Subpage 3 (Address[20–21] = 11) User fetch is permitted
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Figure 8-19, contains the protection mode
—
0
R
25 26
UFP
—
R
818
Description
15
29 30 31
PV G
— —
Freescale Semiconductor