Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 56

Figure
Number
20-13 SI Mode Register (SIMODE) ............................................................................................. 20-17
20-14 One Clock Delay from Sync to Data (xFSD = 01) ............................................................. 20-19
20-15 No Delay from Sync to Data (xFSD = 00).......................................................................... 20-19
20-16 Falling Edge (FE) Effect When CE = 1 and xFSD = 01..................................................... 20-20
20-17 Falling Edge (FE) Effect When CE = 0 and xFSD = 01..................................................... 20-20
20-18 Falling Edge (FE) Effect When CE = 1 and xFSD = 00..................................................... 20-21
20-19 Falling Edge (FE) Effect When CE = 0 and xFSD = 00..................................................... 20-22
20-20 SI Clock Route Register (SICR) ......................................................................................... 20-23
20-21 SI Command Register (SICMR) ......................................................................................... 20-24
20-22 SI Status Register (SISTR).................................................................................................. 20-24
20-23 SI RAM Pointer Register (SIRP) ........................................................................................ 20-26
20-24 Dual IDL Bus Application Example................................................................................... 20-27
20-25 ISDN Terminal Adaptor Using IDL.................................................................................... 20-28
20-26 IDL Bus Signals .................................................................................................................. 20-29
20-27 GCI Bus Signals.................................................................................................................. 20-31
20-28 Bank-of-Clocks Selection Logic for NMSI ........................................................................ 20-35
20-29 Baud Rate Generator (BRG) Block Diagram ..................................................................... 20-37
20-30 Baud Rate Generator Configuration Registers (BRGCn) ................................................... 20-38
21-1 SCC Block Diagram.............................................................................................................. 21-2
21-2 GSMR_H—General SCC Mode Register (High Order)....................................................... 21-4
21-3 GSMR_L—General SCC Mode Register (Low Order)........................................................ 21-6
21-4 Data Synchronization Register (DSR) ................................................................................ 21-10
21-5 Transmit-on-Demand Register (TODR) ............................................................................. 21-10
21-6 SCC Buffer Descriptors (BDs)............................................................................................ 21-12
21-7 SCCx Buffer Descriptor and Buffer Structure .................................................................... 21-12
21-8 Function Code Registers (RFCR and TFCR) ..................................................................... 21-15
21-9 Output Delay from RTS Asserted for Synchronous Protocols ........................................... 21-17
21-10 Output Delay from CTS Asserted for Synchronous Protocols ........................................... 21-18
21-11 CTS Lost in Synchronous Protocols ................................................................................... 21-19
21-12 Using CD to Control Synchronous Protocol Reception...................................................... 21-20
21-13 DPLL Receiver Block Diagram .......................................................................................... 21-21
21-14 DPLL Transmitter Block Diagram...................................................................................... 21-22
21-15 DPLL Encoding Examples.................................................................................................. 21-24
22-1 UART Character Format ....................................................................................................... 22-1
22-2 Two UART Multidrop Configurations.................................................................................. 22-7
22-3 Control Character Table, RCCM, and RCCR ....................................................................... 22-8
22-4 Transmit Out-of-Sequence Register (TOSEQ) ................................................................... 22-10
22-5 Data Synchronization Register (DSR) ................................................................................ 22-11
22-6 Protocol-Specific Mode Register for UART (PSMR) ........................................................ 22-13
22-7 SCC UART Receiving using RxBDs.................................................................................. 22-16
22-8 SCC UART RxBD .............................................................................................................. 22-17
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Figures
Title
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Page
Number
Freescale Semiconductor