Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 590

SDMA Channels and IDMA Emulation
CLK
TS
TA
19.2 SDMA Registers
All SDMA channels share one configuration register (SDCR), a status register (SDSR), a mask register
(SDMR), and a read-only, address register (SDAR). The configuration of each serial controller also affects
their dedicated SDMA channels' behavior. The following sub-sections describe the SDMA registers.
19.2.1 SDMA Configuration Register (SDCR)
The SDMA configuration register (SDCR) configures all 22 virtual SDMA channels. It controls the
channels' U-bus priority level and freeze-signal (FRZ) behavior. It is always read/write in supervisor
mode, even though writing to the SDCR is not recommended unless the CPM is disabled. This register is
affected by HRESET but is not affected by SRESET.
0
Field
Reset
R/W
Addr
16 17
Field — FRZ
Reset
R/W R R/W
Addr
19-4
Other Cycle SDMA Cycle
SDMA Internally
Requests the Bus
Figure 19-2. SDMA U-Bus Arbitration (Cycle Steal)
0000_0000_0000_0000
18
0
0000_0000_0000_0000
Figure 19-3. SDMA Configuration Register (SDCR)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Other Cycle
Figure 19-3 shows the register format.
—
R
IMMR + 0x030
25 26
1
R/W
IMMR + 0x032
15
27 28 29 30 31
0
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