Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 165

0
Field
Reset
R/W
16 17 18
Field EE PR FP
Reset 0 0 0
R/W
1
The reset value of IP is determined by the IIP bit (bit 2) in the hard reset configuration word. See
Reset Configuration Word."
When an exception is taken, most MSR bits are saved in the SRR1 and the MSR is reconfigured with the
state of the exception handler using the values in
"Exception Latency."
After a hard reset, MSR[IP] takes the value specified in hard reset configuration word. See
Section 11.3.1.1, "Hard Reset Configuration Word."
Bits Name
0–12 — Reserved
13 — Reserved. Must be written as a 0.
14 — Reserved
15 ILE Exception little-endian mode. When an exception occurs, this bit is copied into MSR[LE] to select
the endian mode for the context established by the exception.
1
16 EE External interrupt enable
0 The processor delays recognition of external and decrementer interrupt conditions.
1 The processor is enabled to take an external or decrementer interrupt.
1
17 PR Privilege level
0 The processor can execute both user- and supervisor-level instructions.
1 The processor can only execute user-level instructions.
1
18 FP Floating-point available
0 The processor prevents dispatch of floating-point instructions, including floating-point loads,
stores, and moves.
1 The processor can execute floating-point instructions. (This setting is invalid on the MPC885.)
1
19 ME Machine check enable
0 Machine check exceptions are disabled.
1 Machine check exceptions are enabled.
20 — Reserved
Freescale Semiconductor
—
0000_0000_0000_0000
19 20 21 22
ME — SE BE
0 0 0 0
Subsequent soft resets cause IP to revert to the value latched during hard reset configuration.
Machine State Register (MSR)
Figure 4-3.
Figure
Table 4-8. MSR Field Descriptions
MPC885 PowerQUICC Family Reference Manual, Rev. 2
R/W
23 24 25 26 27
— IP IR DR
1
0 0 0 0 0
R/W
4-3. This process is described in
MSR bits are described in
Description
MPC8xx Core Register Set
12 13 14 15
– — ILE
28 29 30 31
— RI LE
0 0 0
Section 11.3.1.1, "Hard
Section 6.1.6,
Table 4-8.
4-7