Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 316

System Interface Unit
10.10.3 PIT Register (PITR)
The PIT register (PITR) is a read-only register that shows the current value in the periodic interrupt down
counter. Writes to PITR do not affect it; reads do not affect the counter.
0
Field
Reset
R/W
Addr
16
Field
Reset
R/W
Addr
Table 10-22 describes PITR fields.
Bits Name
0–15 PIT Periodic interrupt timing count. Holds the current count remaining for the periodic timer. Writes do
not affect PIT.
16–31 — Reserved, should be cleared.
10.11 General SIU Timers Operation
The following sections provide detailed information about the operation of the SIU timers.
10.11.1 Freeze Operation
The external FRZ signal is asserted as a result of entry into debug mode, or as a result of actions performed
by a software monitor debugger as described in
is asserted, the clocks to the software watchdog, PIT, timebase counter, and decrementer can be disabled.
This is controlled by the associated bits in the control register of each timer. If they are programmed to
stop counting when FRZ is asserted, the counters maintain their values until FRZ is negated. The bus
monitor, however, will be enabled regardless of this signal's state.
10-28
(IMMR & 0xFFFF0000) + 0x248
(IMMR & 0xFFFF0000) + 0x24A
Figure 10-26. PIT Register (PITR)
Table 10-22. PITR Field Descriptions
Section 53.4.1, "Freeze Indication."
MPC885 PowerQUICC Family Reference Manual, Rev. 2
PIT
—
R
—
-
R
Description
15
31
When the FRZ signal
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