Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 664

Serial Communications Controllers
When RTS is asserted, if CTS is not already asserted, delays to the first data bit depend on when CTS is
asserted. Figure 21-10 shows that the delay between CTS and the data can be approximately 0.5 to 1 bit
times or 0 bit times, depending on GSMR_H[CTSS].
TCLK
TXD
(Output)
RTS
(Output)
CTS
(Input)
NOTE:
1. GSMR_H[CTSS] = 0. CTSP is a don't care.
TCLK
TXD
(Output)
RTS
(Output)
CTS
(Input)
NOTE:
1. GSMR_H[CTSS] = 1. CTSP is a don't care.
Figure 21-10. Output Delay from CTS Asserted for Synchronous Protocols
If CTS is programmed to envelope data, negating it during frame transmission causes a CTS lost error.
Negating CTS forces RTS high and Tx data to become idle. If GSMR_H[CTSS] is zero, the SCC must
sample CTS before a CTS lost is recognized; otherwise, the negation of CTS immediately causes the CTS
lost condition. See Figure
21-18
First Bit of Frame Data
CTS Sampled Low Here
First Bit of Frame Data
21-11.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Last Bit of Frame Data
Last Bit of Frame Data
Freescale Semiconductor