Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 382

External Bus Interface
Figure 13-5 shows the basic timing for a single-beat read cycles with no wait states.
CLKOUT
BR
BG
BB
A[0:31]
R/W
TSIZ[0:1], AT[0:3]
BURST
TS
Data
TA
Figure 13-5. Basic Timing: Single-Beat Read Cycle, Zero Wait States
13-8
Receive BG and BB negated
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Assert BB, drive address and assert TS
Data is Valid
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