Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 644

Serial Interface
0
Field
Reset
R/W
Addr
16 17
Field EXTC ATB
Reset
R/W
Addr
Figure 20-30. Baud Rate Generator Configuration Registers (BRGCn)
These registers are affected by HRESET but are not affected by SRESET.
BRGCn fields.
Bits Name
0–13 — Reserved, should be cleared.
14 RST Reset BRG. Performs a software reset of the BRG identical to that of an external reset. A reset
disables the BRG and drives BRGO high. This is externally visible only if BRGO is connected to the
corresponding parallel I/O pin.
0 Enable the BRG
1 Reset the BRG (software reset)
15 EN Enable BRG count. Used to dynamically stop the BRG from counting—useful for low-power modes.
0 Stop all clocks to the BRG
1 Enable clocks to the BRG
16–17 EXTC External clock source. Selects the BRG input clock.
00 BRGCLK (internal clock generated by the clock synthesizer in the SIU).
01 CLK2
10 CLK6
11 Reserved
18 ATB Autobaud. Selects autobaud operation for BRG n on the corresponding RXD n . ATB must remain zero
until the SCC receives the three Rx clocks. Then the user must set ATB to obtain the correct baud
rate. After the baud rate is obtained and locked, it is indicated by setting AB in the UART event
register. See
0 Normal operation of the BRG
1 When RXD goes low, the BRG determines the length of the start bit and synchronizes the BRG
to the actual baud rate.
20-38
0x9F0 (BRGC1), 0x9F4 (BRGC2), 0x9F8 (BRGC3), 0x9FC (BRGC4)
18 19
0x9F2 (BRGC1), 0x9F6 (BRGC2), 0x9FA (BRGC3), 0x9FE (BRGC4)
Table 20-13. BRGC n Field Descriptions
Section 20.4.2, "Autobaud Operation on the SCC UART."
MPC885 PowerQUICC Family Reference Manual, Rev. 2
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0
R/W
CD
0
R/W
Description
13 14 15
RST EN
30 31
DIV16
Table 20-13 describes the
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